High speed sense amplifier for MOS random access memory

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

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307238, 307279, 307356, 307DIG3, 365203, 365205, H03K 520, H03K 518, H03K 3286, G11C 1140

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040817016

ABSTRACT:
A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with bistable sense amplifier circuits at the center of each column. The load transistors in each bistable circuit have clock voltages applied to their gates after an initial sensing period, so the initial sensing is done without loads for the bistable circuit. After this initial period, the load transistors are turned on by boosting capacitors. Then, fixed biased transistors shunting the gates of the load device to the digit lines function to turn off the load device on the zero logic level side.

REFERENCES:
patent: 3771147 (1973-11-01), Boll et al.
patent: 3806898 (1974-04-01), Askin
patent: 3949381 (1976-04-01), Dennard et al.
patent: 3992704 (1976-11-01), Kantz
patent: 3993917 (1976-11-01), Kalter
patent: 4010453 (1977-03-01), Lewis
Chu et al., "Low-Power, High-Speed Sense Latch;" IBM Tech. Discl. Bull.; vol. 17, No. 9, pp. 2582-2583; 2/1975.
Bishop et al., "High-Sensitivity, High-Speed FET Sense Latch," IBM Tech. Discl. Bull.; vol. 18, No. 4, pp. 1021-1022, 9/1975.
Barsuhn et al., "Semiconductor Storage Circuit Utilizing Two Device Memory Cells," IBM Tech. Discl. Bull.; vol. 18, No. 3, pp. 786-787; 8/1975.
Lewis, "Memory Sense Amplifier," IBM Tech. Discl. Bull.; vol. 18, No. 11, pp. 3601-3602; 4/1976.

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