High-speed sense amplifier circuit with inhibit capability

Details High-speed sense amplifier circuit with inhibit capability High-speed sense amplifier circuit with inhibit capability

1983-06-30

1986-02-11

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307362, 307495, H03K 1762

Patent

active

045700907

ABSTRACT:
A sense amplifier circuit for use with a directory memory chip in which the output of a corresponding memory cell is sensed and output signals representing the sensed bit state are provided to first and second output ports. The signal provided to the first output port can be selectively inhibited, although, when not inhibited, the signals applied to the first and second output ports occur simultaneously. The inhibiting function may be performed by a dual-emitter circuit and switchable current source in one of two sense amplifiers.

REFERENCES:
patent: 3473149 (1969-10-01), Ashley
patent: 3594590 (1971-07-01), Smith
patent: 3617772 (1971-11-01), Tertel
patent: 3760194 (1973-09-01), Lutz et al.
patent: 3789243 (1974-01-01), Donofrio et al.
patent: 4099070 (1978-07-01), Reinert
patent: 4125877 (1978-11-01), Reinert
patent: 4193127 (1980-03-01), Gersbach
patent: 4287575 (1981-09-01), Eardley et al.
patent: 4375039 (1983-02-01), Yamauchi
Chen et al., "Sense Amplifier for Double Density Array", IBM Tech. Disc. Bull., vol. 24, No. 11A, Apr. 1982, pp. 5651-5653.
Chen, "Bit-Select Sense Amplifier", IBM Tech. Disc. Bull., vol. 24, No. 11A, Apr. 1982, pp. 5654-5656.

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