Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2002-10-28
2004-09-28
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
Reexamination Certificate
active
06798252
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a high-speed sense current amplifier with a low power consumption for a memory cell.
2. Description of the Related Art
Semiconductor memories are binary data memories in which the individual memory cells SZ are arranged in matrix form and comprise semiconductor components, in particular transistors. In this case, the memory cells SZ are connected to word lines WL and bit lines BL, running perpendicularly thereto. The matrix contains n*m memory cells. The addressing, i.e. the selection of a memory cell SZ or a memory word, is effected by activation of the word lines WL. In this case, the addressing is performed by an address decoder which, given n external address lines, internally generates 2
n
selection signals for word line and bit line selection. The data information items contained in the memory cells SZ are read out via a sense amplifier.
FIG. 1
schematically shows the construction of a semiconductor memory arrangement. The address decoder D is connected to an address bus AR and decodes the addressing signal present on the address bus AR for the selection of memory cells SZ within the semiconductor memory. The read-out data contained in the memory cells SZ pass via memory signal lines to a multiplexer MUX, which is connected to the sense amplifier on the output side. The sense amplifier amplifies the received memory signal and outputs it to a data bus DR via an output buffer P.
FIG. 2
schematically shows part of a sense current amplifier for the read-out and amplification of the data content contained in a memory cell SZ, according to the prior art.
The memory cell SZ contains a data bit information item, the memory cell SZ being in a logic low state L(low) or a logic high state H(high). The memory cell SZ may be a RAM memory cell or a ROM memory cell. The memory cell SZ is addressed via a word line WL leading away from the decoder D and outputs the data content contained in it via the bit line BL. In this case, a memory signal current I
BL
flows via the memory signal line or bit line BL to the multiplexer MUX. The memory signal current I
BL
is zero if the memory cell SZ is in a logic low state L. If the memory cell SZ is in a logic high state H, a predetermined memory signal current I
BL
flows. The bit line BL has a line capacitance and can be precharged or recharged via a charging circuit comprising e.g. a clocked MOSFET transistor. The multiplexer MUX is controlled in a manner dependent on a selection signal SS
1
and through-connects the memory signal line BL to the input E of the sense current amplifier LSV. The sense current amplifier LSV contains a current mirror circuit which is supplied with a supply voltage V
DD
. On the output side, the current mirror circuit is connected to a node which is connected to the output A of the sense current amplifier LSV according to the prior art. The current mirror circuit amplifies the memory signal current I
BL
received via the input E with a constant factor K and outputs the amplified current K·I
BL
at the output A of the sense current amplifier LSV. Furthermore, at a reference current source terminal REF, a reference current source is connected to the current node connected to the output A. The reference current source according to the prior art is likewise connected to the supply voltage V
DD
and can be selected by means of a selection signal SS
2
. The summation current node has an intrinsic capacitance C
A
.
FIG. 3
shows the reference current source according to the prior art as illustrated in FIG.
2
. The reference current source contains a plurality of N-MOSFET transistors T
1
, T
2
, and T
3
. The N-MOSFET transistor T
1
of the reference current source generates a constant current in a manner dependent on the selection signal SS
2
. If the selection signal SS
2
is logic 0, the constant current I
K
of the MOSFET transistor T
1
is zero. Conversely, if the selection signal SS
2
is switched on, a constant current I
K
ø with a specific constant current magnitude flows through the N-MOSFET transistor T
1
. The following hold true:
I
K
=0 if
SS
2
=1
I
K
=I
Kø
if
SS
2
=ø (1)
The reference current source according to the prior art furthermore contains a current mirror circuit comprising the two N-MOSFET transistors T
2
and T
3
, the two gate terminals of the two N-MOSFET transistors T
2
and T
3
being connected to one another and having a direct connection to the source terminal of the N-MOSFET transistor T
1
. The constant current I
Kø
is mirrored by the current mirror circuit T
2
and T
3
, the current gain being determined by the current channel width/length ratio W/L of the two transistors T
2
and T
3
.
The N-MOSFET T
2
of the current mirror circuit has a source terminal connected to ground and a drain terminal connected to the reference current terminal REF. The current mirror circuit T
2
and T
3
generates a constant reference current I
REFø
at the reference current terminal REF, the following holding true:
I
REF
∅
=
μ
Cox
W
/
L
2
(
V
GS
-
V
T
)
2
(
2
)
where:
W/L is the channel width/length ratio of the transistor T
2
,
C
ox
is the capacitance of the dielectric,
V
T
is the threshold voltage of the transistor T
2
, and
V
GS
is the gate/source voltage of the transistor T
2
.
Since the voltage V
GS
between the gate and the source of the transistor T
2
is constant and the remaining quantities are also predetermined, the reference current I
REFO
generated by the reference current source is constant.
FIG. 4
shows the current mirror circuit contained in the sense current amplifier according to the prior art. The current mirror circuit contains two P-MOSFETs T
4
and T
5
, whose gate terminals are connected to one another and are connected to the input E of the current mirror circuit. The two drain terminals of the two P-MOSFETS T
4
and T
5
are connected to the supply voltage potential V
DD
. The source terminal of the first P-MOSFET T
4
is likewise connected to the signal input E of the current mirror circuit and receives the memory signal current I
BL
. The channel width/length ratios W/L of the two P-MOSFETs T
4
and T
5
are defined in such a way that the memory signal current I
BL
is output amplified by a fixed gain factor K at the source terminal of the second P-MOSFET T
5
.
In the conventional sense current amplifier, as illustrated in
FIG. 2
, the following holds true for the output voltage at the output A:
VA=VDD
if
K*I
BL
≧I
REFø
VA
=ø if
K*I
BL
<I
REFø
(3)
In the conventional sense current amplifier according to the prior art, as illustrated in
FIG. 2
, one disadvantage is that a high reading speed for the readout of the memory cell SZ and a low power consumption P of the sense current amplifier LSV cannot be achieved simultaneously. This will be explained below with reference to the signal profile illustrated in FIG.
5
. If the memory cell SZ is not being read, the output A of the sense current amplifier LSV is at a predetermined high potential corresponding to the supply voltage V
DD
. If the memory cell SZ is not being read, the memory signal current I
BL
is 0.
At the instant t
1
, a read operation A is initiated in the example illustrated in
FIG. 5
, in the course of which a memory cell SZ which is in a logic low state L is read. When reading from a memory cell SZ which assumes a logic low state L, a memory signal current I
BL
of zero is generated, so that an output current of K*I
BL
which is lower than the constant reference current I
REPø
flowing into the reference current source is also output at the output of the current mirror circuit. Since the reference current I
REFO
flowing from the current node is greater than the amplified memory signal current (K*I
BL
) flowing into the current node A, the intrinsic or parasitic capacitance C
A
at the output A of the sense current amplifier LSV according to the prior art is discharged, so that the outpu
Ekkart Martin
Ettore Riccio
Moyal Michael
Schulz Dirk
Infineon - Technologies AG
Nu Ton My-Trang
Schiff & Hardin LLP
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