Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2002-09-24
2004-09-14
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S765010
Reexamination Certificate
active
06791316
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a high speed semiconductor test system, and more particularly, to a high speed semiconductor test system having pin cards arranged radially in a test head to achieve equidistance and minimum round-trip-delay time (RTD) between a device under test (DUT) and drivers/comparators on the pin cards.
BACKGROUND OF THE INVENTION
In testing a semiconductor integrated circuit device (IC device) by a semiconductor test system (IC tester), an IC device under test is provided with test patterns (test vectors) produced by an IC tester at its appropriate pins at predetermined test timings. The IC tester receives output signals from the IC device under test in response to the test patterns. The output signals are strobed by strobe signals with predetermined timings and compared with expected data to determine whether the IC device functions correctly.
FIG. 1
is a schematic block diagram showing an example of basic configuration of an IC tester. In the example of
FIG. 1
, a test processor
11
controls an overall operation of the test system through a tester bus. Based on pattern data from the test processor
11
, a pattern generator
12
provides timing data and waveform data to a timing generator
13
and a wave formatter
14
, respectively. A test pattern is produced by the wave formatter
14
with use of the waveform data from the pattern generator
12
and the timing data from the timing generator
13
. The test pattern is supplied to an IC device under test (DUT)
19
through a driver
15
.
An output signal from the DUT
19
resulted from the test pattern is converted to a logic signal by a comparator
16
with reference to predetermined threshold voltage levels. The signal from the comparator
16
is compared with expected value data from the pattern generator
12
by a comparator
17
. The result of the comparison is stored in a failure memory
18
corresponding to the address of the DUT
19
. The driver
15
, the comparator
16
and switches (not shown) for changing pins of the device under test, are provided in a pin electronics (pin card)
20
.
The circuit configuration noted above is provided to each test pin of the semiconductor test system. For testing a large scale integrated circuit, an IC tester has a large number of test pins, such as from 256 to 1024 test pins. Therefore, the IC tester has a large number of pin electronics circuits 20 (drivers and comparators), for example, 256-1024, each being configured as shown in FIG.
1
.
Such pin electronics cards (pin cards) are aligned in a test head of the semiconductor test system (IC tester) as shown in FIG.
2
. Typically, a pin card includes drivers and comparators and other components of IC tester such as a timing generator (clock generator) and a wave formatter of
FIG. 1
for each test pin. As shown in
FIG. 2. a
load board (performance board)
40
is mounted on a test head
30
of the IC tester. The IC device under test (DUT)
19
is mounted on the load board
40
through an IC socket (test socket)
45
. In
FIG. 2
, as is well known in the art, an integrated circuit (DUT) is configured by an IC chip which is typically encapsulated by an IC package.
The general speed specifications of present day semiconductor integrated circuits (ICs) are on the order of GHz (giga-hertz). It is expected that the speed will increase to tens of GHz in the next few years. In order to test those high speed semiconductor integrated circuits, it is desirable that test patterns (test vectors) be applied at the speed corresponding to the speed of the ICs to be tested. Executing functional test vectors at the IC chip's specified speed at which it will operate is referred to as “at-speed testing” in the industry.
In the structure of
FIG. 2
, at chip operating speeds of 250 MHz or higher, a round-trip-delay (RTD) from the driver to DUT and back to the comparator prohibits the application of high-speed test vectors. As illustrated in
FIG. 2
, the path of RTD contains the device pin of DUT
19
, socket pin of IC socket
45
, trace on the load board
40
and the wire in the test head
30
to and from the driver
15
and comparator
16
. In general, RTD is on the order of 2 ns (nanosecond) in the present day semiconductor test systems (IC testers).
The RTD time puts a restriction on the speed by which an IC tester can apply test vectors to a bi-directional pin of DUT. A bi-directional pin is an I/O (input/output) pin that switches between input and output modes. In testing such a bi-directional pin, the path between the device pin and the IC tester is shared between the tester driver
15
and tester comparator
16
. Thus, the test pattern from the tester driver
15
is applied to the DUT
19
and the resultant signal is sent back to the comparator
16
. Therefore, the drive signal from the tester driver
15
to the DUT
19
must wait until the DUT output data has reached the tester comparator
16
and the tri-state condition involved in the bi-direction pin has had enough time to propagate through this one way path.
Thus, to test a bi-directional pin of DUT, the switching speed from the input state to the output state of the bi-directional pin should be less than the physical delay over this path.
FIGS. 3A and 3B
illustrate a typical bi-directional signal timing.
FIG. 3A
shows a clock signal in the IC tester and
FIG. 3B
shows a waveform seen at the bi-directional pin of DUT
19
. The waveform of
FIG. 3B
includes various time segments. The maximum frequency at which a tester can test is defined by:
Max Test Frequency=Setup time (A)=Active to tri-state interval time (G)=Data-to-tri-state-transition propagation time till it reaches the comparator (H)=Time for driver signal to reach DUT (I).
Although various time segments are illustrated in
FIG. 3B
, for simplicity and ease of explanation, only the components related to the present invention is explained. In this example, for simplicity, it is assumed that each of the time components H and I is equal to ½ RTD. Again, for simplicity, it is assumed that 1 ns (nanosecond) is incurred for set-up (component A in
FIG. 3B
) and 1 ns is incurred for active to tri-state time (component G in FIG.
3
B). Thus, the total delay of 3 ns is obtained by adding components A, I, G, and H. This means that the maximum test frequency can be about 334 MHz (one tester period or clock of FIG.
3
A=3 ns) even if the IC tester is capable of running the test at a higher speed such as 500 MHz. Thus, the testing speed is limited about 334 MHz despite the capability of the IC tester and the requirement of the DUT.
FIG. 4A
is a perspective view showing an example of inner structure of a test head incorporated in a conventional semiconductor test system (IC tester). In the test head
52
, a plurality of pin cards (pin electronics cards)
54
are mounted on a backplane
51
in a row, i.e., parallel fashion. A load board (performance board)
53
is mounted on the test head
52
where all or most of the pin cards
54
are connected to the load board
53
. The DUT is inserted in an IC socket on the load board
53
and thus is connected the pin cards
54
, although the connections (test fixture) are not shown in
FIG. 4A
to simplify the illustration.
As is apparent from
FIG. 4A
, the test head
52
is normally rectangular in shape in the conventional semiconductor test system. A large number of pin cards
54
are aligned in one direction in a parallel fashion as shown in
FIG. 4B
which is a top view of the test head
52
of FIG.
4
A. The DUT is placed at the center of the test head
52
on the IC socket on the load board
53
.
In
FIG. 4B
, because of the arrangement of the pin cards
54
, the distance from the pin card to the DUT is different for each connection. For example, as shown in
FIG. 4B
, the line
61
connecting the left most pin card
54
to the DUT is much longer than the line
62
connecting the pin card
54
nearest to the DUT. Although only the line
61
and line
62
are shown in the drawings to simplify th
Rajsuman Rochit
Yamoto Hiroaki
Advantest Corp.
Muramatsu & Associates
Nguyen Vinh P.
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