Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Light responsive structure
Reexamination Certificate
2001-04-16
2002-12-31
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Light responsive structure
C257S127000, C438S624000
Reexamination Certificate
active
06501104
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor photodetectors, and more specifically to a high speed semiconductor photodetector and a method of fabricating the photodetector.
2. Description of the Related Art
As disclosed in Japanese Patent Publication 5-82829, a semiconductor photodetector is formed in a mesa structure in which the light-sensitive area is separated from the pad electrode by a V-shaped groove. Because of the V-groove separation, a large surface area is obtained without increasing parasitic capacitance and hence high speed operation of the device is possible. As a reliable material TiPtAu is used for the pad electrode and metal lines. Wet and dry etching processes are available for etching the metal compound. However, because of the absence of appropriate etchant for the composition Pt if wet etching is employed and because of the difficulty to achieve constant etch rate if dry etching is used, a technique known as “liftoff process” is used, instead of the metal etching process. Using the liftoff process, a thick layer of photoresist is patterned on the surface of the mesa structure and then a thin layer of metal is deposited using evaporation. The device is immersed in a solution capable of dissolving the photoresist. The pad and metal lines that were deposited directly on the semiconductor remain, while the metal deposited on the resist lifts off of the device as the resist dissolves.
However, one shortcoming of the liftoff process is poor step coverage. Since the metal evaporation process has a directional characteristic, the metal deposited at stepped portions is thinned and tends to break under stress. Another shortcoming is that the Au of the deposited metal exhibits an undesirable characteristic because its high metalleability causes a burr to occur when the metal on the photoreist is separated from the metal on the semiconductor. As a result, fifty percent of the metal lines actually produced has a poor configuration.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a high speed semiconductor photodetector of high reliability and a method of fabricating the photodetector.
Another object of the present invention is to provide a high speed semiconductor photodetector which can be manufactured with high yield and a method of fabricating the photodetector.
According to one aspect of the present invention, there is provided a semiconductor photodetector comprising a semi-insulating substrate, a first layered-semiconductor mesa structure and a second layered-semiconductor mesa structure formed side by side on the substrate, the first layered-semiconductor mesa structure having a photoactive region and a first electrode on the photoactive region and the second layered-semiconductor mesa structure having a pad electrode, and an interconnect line of laminated metal structure for establishing a connection between the first electrode and the pad electrode.
Specifically, the laminated metal structure comprises a lower metal layer and an upper metal layer, the upper metal layer having a greater thickness than the thickness of the lower metal layer. In one embodiment of the present invention, the interconnect line extends along sidewalls of a valley between the first and second semiconductor mesa structures. In a modified embodiment, the interconnect line extends as a bridge over a void between the first and second semiconductor mesa structures.
According to a second aspect to the present invention, there is provided a method of fabricating a semiconductor photodetector comprising the steps of (a) forming a first layered-semiconductor mesa structure having a photoactive region and a second layer-semiconductor mesa structure side by side on a semi-insulating substrate, (b) enclosing the first and second layered-semiconductor mesa structures with a protective layer, (c) patterning the protective layer to form a contact hole therein and filling the contact hole with conductive material to form a first electrode on the photoactive region, (d) surrounding the first and second layered-semiconductor mesa structures with a photoresist layer by excluding an elongate portion that extends along sidewalls of a valley between the mesa structures, (e) covering the mesa structures and the surrounding photoresist layer with a metal layer, (f) forming on the metal layer a mask having patterns of the first electrode, the elongate portion and a pad electrode on the second mesa structure, (g) selectively depositing conductive material through the mask to form a plurality of metallized regions on the metal layer, (h) removing the mask and patterning the metal layer into a plurality of regions corresponding to the metallized regions by using the metallized regions as a mask, and (i) removing the surrounding photoresist layer. The metallized regions and patterned metal regions form two laminated metal structures for positive and negative electrodes. The elongate portion is deposited with one of the laminated structures.
According to a third aspect, the present invention provides a modified method in which an air bridge process is used for fabricating the interconnect metal line. The modified method comprises the steps of (a) forming a first layered-semiconductor mesa structure having a photoactive region and a second layered-semiconductor mesa structure side by side on a semi-insulating substrate, (b) enclosing the first and second layered-semiconductor mesa structures with a protective layer, (c) patterning the protective layer to form a contact hole therein and filling the contact hole with conductive material to form a first electrode on the photoactive region, (d) surrounding the first and second layered-semiconductor mesa structures with a photoresist layer by filling a valley therebetween with the photoresist layer, (e) covering the mesa structures and the surrounding photoresist layer with a metal layer, (f) forming on the metal layer a mask having patterns of the first electrode, an elongate portion that crosses over the valley and a pad electrode on the second mesa structure, (g) selectively depositing conductive material through the mask to form a plurality of metallized regions on the metal layer, (h) removing the mask and patterning the metal layer into a plurality of metal regions corresponding to the metallized regions by using the metallized regions as a mask, and (i) removing the surrounding photoresist layer. The metallized regions and patterned metal regions form two laminated metal structures for positive and negative electrodes. The valley-crossing elongate portion is composed of one of the laminated structures and takes in the shape of a bridge.
Preferably, the surrounding photoresist layer of the step (d) partially covers edge portions of the mesa structures, and the step (d) comprises the step of hard-baking the photoresist layer to form downwardly sloping contour at inner fringe portions of the surrounding photoresist layer. In a preferred embodiment, the step (h) is performed by using an ion milling process.
REFERENCES:
patent: 6049638 (2000-04-01), Norimatsu et al.
patent: 5-82829 (1993-04-01), None
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