High speed self-adjusting clock recovery circuit with frequency

Details High speed self-adjusting clock recovery circuit with frequency High speed self-adjusting clock recovery circuit with frequency

1996-03-13

1998-05-26

Vo, Don N.

Pulse or digital communications

Systems using alternating or pulsating current

Angle modulation

375322, 375326, 375327, 375371, 329346, 329306, H03K 706, H03K 906

Patent

active

057578575

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The invention relates to the field of clock extraction circuits used in digital communication, and in particular, to a high speed self-adjusting clock extraction circuit used with nonreturn-to-zero (NRZ) data.
2. Description of the Prior Art
Communication of information using digital methods is preferable in most instances to analog methods due to the immunity to interference, error correcting channel coding methodologies available, time division multiplexing of signals for increased channel usage, and source coding for efficient information transfer, which is available in the digital format. Whenever information is transmitted digitally, it is broken into a sequence of symbols belonging to a finite alphabet. In order to receive these signals, the receiver must be synchronized with the incoming data such that the information can be sampled at the appropriate time.
Often there is a hierarchy of synchronization that must be performed. For example, in a video system, a receiver must recognize individual bits. Therefore, a clock in a video system must exist at the bit rate to provide bit level synchronization. Bits are ordered into larger groups, called bytes, which in turn are reordered into even still larger groups designated as lines, which in turn are organized into larger groups still defined as frames. For video operation, a receiver must know when the beginning of each frame occurs. Usually, synchronization at the frame and line levels is determined by software and system protocols. However, at the lowest level, bit synchronization must occur, otherwise there will be no intelligible information available to make software controlled decisions at higher levels.
A common modulation format for digital data is the nonreturn to zero (NRZ) format, which is also known on-off keying because the signal is on for one binary state, and off for the other. The binary NRZ signal makes transitions from one binary state to the other only when there is a change in the bit value. For example, the signal 111 in NRZ format will be an unbroken high logic level for three bit intervals. If the signal should then become 1110, a negative transition will occur after three bit intervals and a single bit interval will be at the low logic level where the signal will remain until a logical 1 is again to be represented.
The advantages of NRZ format is that is does not occupy as much bandwidth as other digital formatting schemes, such as return-to-zero (RZ) or Manchester coding. Further, about 90 percent of the signal energy of NRZ data is contained within the bit rate frequency, B.sub.T, and about 80 percent of the energy lies within a frequency of B.sub.T/2. convenient way to picture random digital data is to superimpose sections of the digital signal separated by integer multiples of the bit period T. Such a plot is called an "eye diagram" and illustrates the structure inherent in random data. FIG. 1 is a block diagram of a typical prior art fiber optic receiver, generally denoted by reference numeral 10, associated with eye diagrams of the data and clock signals at various nodes within the circuit. For example, the eye diagram of FIG. 2a is the input data signal provided at input 10 to preamplifier 14. The dispersion of the optical fiber typically band limits the data, therefore, the square wave NRZ data is modeled in this example as having sinusoidal transitions between the high and low logic states. The input signal is shown without noise and is very weak so that it must be amplified by preamplifier 14, where it is unavoidably corrupted by noise so that the form at output 16 appears as shown in the eye diagram of FIG. 2b. The noise of the preamplifier generally determines the overall signal-to-noise ratio of the receiver, as the input signal is weakest at input 12 of receiver circuit 10.
The signal is again amplified by a post-amplifier 18, which performs noise filtering and has an automatic gain control function to keep the input of the clock recovering decision circuit foll

REFERENCES:
patent: 3626298 (1971-12-01), Paine
patent: 4570125 (1986-02-01), Gibson
patent: 4604755 (1986-08-01), Murray
patent: 4879728 (1989-11-01), Tarallo
patent: 4926447 (1990-05-01), Corsetto et al.
patent: 4949357 (1990-08-01), Sehier
patent: 5012494 (1991-04-01), Lai et al.
patent: 5233631 (1993-08-01), Labat et al.
patent: 5402449 (1995-03-01), Schultes et al.

Affiliated with

Also associated with

Rating

High speed self-adjusting clock recovery circuit with frequency does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed self-adjusting clock recovery circuit with frequency , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed self-adjusting clock recovery circuit with frequency will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1972745