High speed scrambling at lower clock speeds

Details High speed scrambling at lower clock speeds High speed scrambling at lower clock speeds

1987-06-05

1988-07-05

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 18, 375 1, H04J 302

Patent

active

047559870

ABSTRACT:
Circuitry generates a plurality of differently-phased m-sequences (or pseudo-random sequences) for scrambling/descrambling of all tributary data signals at a multiplexer/demultiplexer. By scrambling/descrambling at the tributary levels and thus at the lower tributary clock rates, less complex circuitry can be employed, and by properly selecting the tributary scrambling sequences in accordance with the teachings of this invention, a desired high speed line sequence can be attained.

REFERENCES:
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patent: 4134071 (1979-01-01), Ohnsorge
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