High speed Schmitt Trigger with low supply voltage

Details High speed Schmitt Trigger with low supply voltage High speed Schmitt Trigger with low supply voltage

2000-08-30

2002-08-13

Smith, Matthew (Department: 2825)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S206000

Reexamination Certificate

active

06433602

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to electrical circuits, more specifically to integrated circuit (“IC”) buffers, and more particularly to a high speed complementary metal oxide silicon (“CMOS”) buffer with monotonic hysteresis capable of working with a very low power supply voltage (“Vcc”), yet having a small trip point range.
2. Description of Related Art
A Schmitt Trigger is an electronic circuit well known in the state of the art and often used to turn a signal having a slow or asymmetrical transition into a signal with a sharp transition region. Schmitt Triggers are useful of IC inputs to clean up input change signals and to do signal level transitions. However, a Schmitt Trigger is generally slower than an inverter circuit of the same operational power. Moreover, a Schmitt trigger uses more current because several wide, big, integrated circuit elements are simultaneously in an ON-state for a relatively long time period. In practice they are not easily optimized for high speed circuitry and they do not provide a “monotonic” hysteresis (never increasing nor decreasing as independent variables increase or decrease) over a wide range of integrated circuit power supply potential, Vcc, range (e.g., about 1.4-volts to 3.6-volts); the lower the Vcc, the worse the performance. In fact, in the state of the art of IC design the call for lower power consumption in much denser IC chip designs is constant; Vcc is being reduced at a much faster rate than in the past.
FIG. 1
(Prior Art) is an electrical schematic for a conventional Schmitt Trigger. Four, stacked, parallel input, metal-oxide-silicon field effect transistors (“MOSFET”) P
1
, P
2
, N
1
, and N
2
are coupled by their respective gate electrodes to the trigger input (“IN”); respective source/drain electrodes are connected in series. Based on the transition of the signal IN, one of the pair will generate a signal (“Vfp” or “Vfn” where “Vf” is determined by the transistor size ratio P
3
/P
1
and N
3
/N
1
) to the related respective output transistor P
3
or N
3
, connected to generate the output signal “OUT” having a sharp, clean transition between levels. In operation, if the output node, OUT, is low, then the p-channel output transistor P
3
is ON and the n-channel output transistor N
3
is OFF; the p-channel input transistors P
2
, P
3
dictate the trip point. If the output is HIGH, the output n-channel transistor N
3
is ON and the p-channel output transistor P
3
is OFF; the n-channel input transistors N
2
, N
3
dictate the trip point; and, p-channel input transistors P
1
, P
2
are ON, providing a direct current (“DC”) path to Vcc. Assuming that OUT is HIGH and that IN is LOW, the n-channel input transistors N
1
and N
2
are OFF and the n-channel output transistor N
3
is ON. The node at Vfn floats to Vfn=Vcc-Vtn, where Vt is transistor turn-on voltage; thus, If the IN signal has a voltage, Vin, less than the Vtn of the n-channel input transistor N
1
(Vin<Vtn
1
), Vfn remains at Vcc
14
Vtn. As Vin increases, n-channel input transistor N
1
begins to turn on and Vfn starts to fall toward Vss, where Vss is zero volts. The trip point is defined when Vin=Vtn2+Vfn, that is, when n-channel input transistor N
2
starts to turn ON. As the second n-channel input transistor N
2
turns ON, the output starts to move toward Vss, causing the n-channel output transistor N
3
to start turning OFF. In turn, this causes Vfn to fall, turning the n-channel input transistor N
2
further toward its ON state. This continues until the n-channel output transistor N
3
is totally OFF and both n-channel input transistors N
1
, N
2
are totally ON. This “positive feedback” causes the trip point to be well defined. At the HIGH trip point Vfn=Vtrip-Vtn. Since the n-channel input transistor N
2
is used as a switch, it has a size much bigger than the other n-channel transistor N
1
. This inherently makes the switching slower. (A similar analysis applies to the p-channel side of this Schmitt Trigger when IN is HIGH and OUT is LOW). By its design, it is not adaptable to high speed functionality since effective switching resistances of MOSFETS are difficult to reduce without changing the trip point. The circuit hysteresis is dependent on Vcc and at very low Vcc levels does not work properly.
FIG. 2
shows a more compact circuit design for another conventional Schmitt Trigger. A basic inverter latch circuit is employed in which two series connected transistor pairs P
1
/N
1
and P
2
/N
2
provide a higher speed performance. However, the switching point voltages of this circuit design are more difficult to predict, especially with respect to keeping a monotonic hysteresis over a wide range of Vcc. Input transistors P
1
and N
1
size ratio dictates the nominal trip point. The input transistors P
1
, N
1
are relatively large devices for speed, having relatively short channel lengths; whereas, output transistors P
2
, N
2
are relatively small devices with relatively long channel lengths. When IN is LOW, the first stage output, “OUT
A
,” is HIGH and the second stage output, “OUT
B
,” is LOW, turning the p-channel output transistor P
2
ON. As the input rises, the n-channel input transistor N
1
has to overcome not only the bias of the p-channel input transistor P
1
where Vgs (“gate-source”) is reducing, but also a weak sized p-channel output transistor P
2
where Vgs=Vcc. When IN is going HIGH to LOW, initially OUT
A
is LOW and OUT
B
is HIGH. MOSFET N
2
is ON and MOSFET P
2
is OFF. MOSFET P
1
starts to turn ON and has to overcome MOSFET N
2
where Vgs=Vcc and MOSFET N
1
. Thus, the main P
1
/N
1
inverter has to fight P
2
/N
2
reducing transition speed substantially. While this circuit is faster than that shown in
FIG. 1
, there are substantive fabrication issues. The mismatch in size between the input and output transistors relates directly to a mismatch in respective Vt; this causes more process variations on the trip points and hysteresis characteristic. Again, with a wide range Vcc designs, the hysteresis is not monotonic and trip points are difficult to define.
There is a need to have an IC input buffer design adaptable to a supply voltage which can vary in order to provide a common interface at the chip boundary. The input buffer design should provide relatively high speed (that is, have a low signal propagation delay time) have a hysteresis that is relatively independent of process Vcc and is substantially monotonic regardless of Vcc change.
SUMMARY OF THE INVENTION
In its basic aspects, the present invention provides a CMOS Schmitt Trigger device including: an input stage forming an inverter, having a pair of input stage CMOS devices, for receiving an input signal; and an output stage, having a first output stage device in parallel with the input stage, the first output stage device having a pair of first output stage CMOS devices coupled to the input stage CMOS devices such that the pair of second stage CMOS devices add to the respective input stage CMOS devices only one at time for changing the trip point of the Schmitt Trigger device, and having a second output stage device connected to the first output stage device for driving an output node.
In another aspect, the present invention provides an integrated circuit buffer device having a circuit input node and a circuit output node, including: connected to the circuit input node, an inverter circuit first stage having a first trip point; connected to the inverter circuit first stage, an inverter circuit second stage wherein said second stage is additive to said inverter circuit first stage for changing said trip point and wherein said first stage and said second stage are connected in parallel having a first output node; an inverter connecting said first output node to said circuit output node; and connected in series to the inverter circuit second stage, a output stage device connected to the circuit output node, wherein said output stage device has discrete component sizes substa

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