High speed sampling receiver with reduced output impedance

Details High speed sampling receiver with reduced output impedance High speed sampling receiver with reduced output impedance

2005-07-26

2005-07-26

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S057000, C327S217000, C327S218000

Reexamination Certificate

active

06922083

ABSTRACT:
A sampling receiver includes: at least one slave latch circuit; and at least one master latch circuit which further includes: at least one differential input transistor pair, and at least one bistable circuit. Output terminals of the at least one differential input transistor pair and output terminals of the at least one bistable circuit are coupled to the at least one slave latch circuit but in parallel to each other with reference to the at least one slave latch circuit for the purpose of reducing an output impedance to allow the sampling receiver to exhibit a high speed latch operation.

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patent: 2001-0002870 (2001-01-01), None

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