High-speed sampling architectures

Details High-speed sampling architectures High-speed sampling architectures

2006-03-21

2006-03-21

Nguyen, Linh Van (Department: 2819)

Coded data generation or conversion

Sample and hold

C341S123000

Reexamination Certificate

active

07015842

ABSTRACT:
A high-speed sampling system and an analog to digital converter are disclosed. One embodiment of a method of sampling a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i−1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub-samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i−1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.

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Gabriele Manganaro, An Improved Phase Clock Generator for Interleaved and Double-Sampled Switched-Capacitor Circuits, 2001 IEEE, no month.

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