High speed sampling and digitizing system requiring no hold circ

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

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341122, H03M 136

Patent

active

051344033

ABSTRACT:
Disclosed is an analog to digital conversion system that converts high speed analog signals to digital values without using a hold circuit. The system has a narrow aperture sampling circuit that samples an input signal and feeds the sampled signal to a capacitor. A resistor in parallel with the capacitor discharges the capacitor at a predetermined rate, thus the capacitor does not hold the sampled signal. The discharging signal output of the capacitor-resistor circuit is amplified and then filtered using a low-pass filter, which has essentially linear phase shift and no undershoot. The filtered signal is then amplified and fed to a flash analog to digital converter which converts the signal into a digital value. The low-pass filter creates a Gaussian output and the converter is timed to convert the signal at the peak of the filter output.

REFERENCES:
patent: 3430072 (1969-02-01), Stevens
patent: 3581305 (1971-05-01), Howlett
patent: 3820033 (1974-06-01), Iwata
patent: 4183016 (1980-01-01), Sawagata
patent: 4584559 (1986-04-01), Penney
Hnatek, Eugene R., A User's Handbook of D/A and A/D Converters, pp. 369-374, 1976.
"A 1-GHz 6-bit ADC System", Ken Poulton et al., IEEE Journal of Solid State Circuits, vol. SC-22, No. 6, Dec. 1987, pp. 962-970.
"A Complete Monolithic Sample/Hold Amplifier", Kenneth R. Stafford et al., IEEE Journal of Solid State Circuits, vol. SC-9, No. 6, Dec. 1974, pp. 381-387.

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