High speed resettable dynamic counter

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

307200B, 307220C, 307279, 328 48, H03K 2308, H03K 2132, H03K 2136, H03K 3353

Patent

active

041818628

ABSTRACT:
A counter stage includes a clocked transmission gate which, when turned on, couples the output of the stage back to its input. A resetting circuit is connected to the input of the stage for selectively clamping the input to a fixed voltage level representative of a logic one or a logic zero. The resetting circuit is enabled only when the clocked transmission gate is turned off, whereby no current can flow from, or to, the output via the resetting means. This enables high speed of reset since the input of the stage is then easily discharged (or charged) to the selected fixed level via the resetting circuit.

REFERENCES:
patent: 3560998 (1971-02-01), Walton
patent: 3823551 (1974-07-01), Riehl
patent: 3887822 (1975-06-01), Suzuki
patent: 3930169 (1975-12-01), Kuhn, Jr.
patent: 3973139 (1976-08-01), Dingwall
patent: 4002926 (1977-01-01), Moyer
patent: 4114049 (1978-09-01), Suzuki
patent: 4124807 (1978-11-01), Herber

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

High speed resettable dynamic counter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed resettable dynamic counter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed resettable dynamic counter will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2121595

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.