High speed register file organization for a pipelined computer a

Details High speed register file organization for a pipelined computer a High speed register file organization for a pipelined computer a

1998-03-10

2000-08-15

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Processing architecture

Long instruction word

364 63, 36423005, 36418904, G06F 900

Patent

active

061051233

ABSTRACT:
A register file organization for a pipelined microprocessor is shown which includes a pipestage register interposed a global bit line and a register cell array of the register file in order to separate the delay associated with driving the global bit line, and devices attached to the global bit line, into a separate pipestage. Another register file organization is shown which includes a pipestage register that is interposed a register cell array and a decoder, which selects a register in the register cell array responsive to an instruction in an instruction register, to separate the decoder function and register cell array access times into different pipestages. The two approaches can be combined to separate the delay associated with the decoder, register cell array and global bit line into different pipestages in order to reduce the pipestage cycle time toward a fundamental minimum for pipelined computer architecture.

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