High speed reference buffer

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Details

C327S543000, C341S155000, C323S313000

Reexamination Certificate

active

06417725

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field Of The Invention
The present invention relates to switched capacitor analog to digital converters (ADCs) and particularly relates to a current sink for use in establishing reference voltages for such ADCs.
2. Background Of The Invention
Switched capacitor ADCs provide efficient high speed conversion of analog signals to digital signals. A representative switched capacitor ADC is shown at
10
in
FIG. 1
, in the form of a multi-stage pipelined ADC. As seen there, ADC
10
includes multiple stages, such as stages
11
and
12
, each providing one or more bits of digital data to a digital correction circuit
15
, which resolves the digital output from each stage into an overall digital output
16
that corresponds to an analog input
17
. Each stage is a switched capacitor circuit operating in response to clock signals such as &phgr;
1
and &phgr;
2
and comparing an analog voltage input to thresholds based on reference signals Vrefp and Vrefn so as to produce the digital outputs as well as a residual analog signal. The residual analog signal is provided as input to the subsequent stage,
For proper operation of ADC
10
, generators are needed for phase and timing signals as well as for reference voltages. These are shown respectively at
20
and
30
of FIG.
1
. Thus, generator
20
for phase and timing signals generates clock signal &phgr;
1
for use during the sample phase of multiple stages
11
and
12
, as well as clock signal &phgr;
2
for use during the amplification phase of multiple stages
11
and
12
. Likewise, generator
30
generates reference voltages vrefp and Vrefn for use by multiple stages
11
and
12
. The focus of the present application is on the generator
30
for the reference voltages.
FIG. 2
shows a conventional generator
30
for generating reference voltage Vrefp; a similar circuit shown schematically at
31
is used to generate reference voltage Vrefn. As shown in
FIG. 2
, generator
30
includes a follower
32
connected between voltage source V+ and a current source
35
which, in turn, is connected to ground. Follower
32
is driven at its gate side by amplifier
34
, which is connected in negative feedback relationship using a reference voltage Vref as a reference and the output Vref as negative feedback. With this arrangement, follower
32
is driven by amplifier
34
so as to provide an output Vrefp with good current capabilities stabilized through negative feedback at a voltage level corresponding to Vref.
Problems arise, however, in use of generators in the form shown at
30
. For example, due to higher frequency switching of generator
30
, and due to noise/glitches generated from MDACS and capacitors which are connected to the reference generator
30
, the amplifier
34
(
FIG. 2
) needs to be very fast, such that it can react quickly to the noise and reset Vrefp to an ideal value (e.g., preferably within a fraction of a clock period). How ever, this would be difficult to achieve for high speed ADcs. Also, amplifier thermal noise would be high in such cases, which would make the Vrefp signal noisy.
An alternative is to design a low bandwidth amplifier to slowly servo Vrefp, and to use an external capacitor (e.g., with a sufficiently large capacitance) to lower the impedance seen by the reference at high frequencies. This alternative may minimize switching glitches and noise, but it also requires extra circuitry, and for example, an extra pin.
Another problem involves the value of Vrefp relative to the source voltage V+. Specifically, because a voltage drop Vgs exists between the gate and source of follower
32
, and because it is not possible for amplifier
34
to output a voltage greater than the supply voltage V+, the value of Vrefp must be lower than V+ by at least an amount equal to Vgs. Typically, Vgs is around 1v, and for adequate design margins, Vrefp is typically set to a value 1.5v less than source voltage V+. This amount of voltage drop, however, is wasteful and unnecessarily limits the dynamic conversion range of multiple stages
11
through
12
.
SUMMARY OF THE INVENTION
It is an object of the present invention to address the foregoing through the provision of an improved generator for reference voltage signals used in a switched capacitor ADC.
In its most preferred form, a generator for reference voltage signals according to the invention is shown at
100
in FIG.
3
. As seen there, the generator includes a follower
132
connected between a voltage source V+ and a current source
135
connected in turn to ground, as well as an amplifier
134
connected in negative feedback relationship with a reference voltage. Negative feedback to amplifier
134
is provided from the output of follower
132
(which forms the reference voltage signals Vrefp or Vrefn that are supplied to the ADC) through a switched capacitor filter
200
.
The output of amplifier
134
is provided to a current sink
300
which drives the gate of follower
132
. Current sink
300
has an effective resistance whose Value is low relative to that of other components in generator
100
, thereby providing a path to sink current through follower
132
and thereby providing increased rejection of noise.
Source voltage for current sink
300
is provided through charge pump
400
. Charge pump
400
operates to increase the effective voltage level of supply voltage V+ for use by current sink
300
, thereby allowing a design in which reference voltages for ADC
10
(such as Vrefp and Vrefn) are set very nearly equal to supply voltage V+ in spite of the voltage drop Vgs of follower
132
.
Although in its preferred form all three components (i.e., charge pump
400
, current sink
300
and switched capacitor filter
200
) are used in the construction of a generator for reference voltages, it is possible to use fewer than all three components, such as only one or two components.
This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiment thereof in connection with the attached drawings.


REFERENCES:
patent: 5162668 (1992-11-01), Chen et al.
patent: 5548205 (1996-08-01), Monticelli
patent: 5648718 (1997-07-01), Edwards
patent: 5706240 (1998-01-01), Fiocchi et al.
patent: 5852359 (1998-12-01), Callahan, Jr. et al.
patent: 5909109 (1999-06-01), Philips
patent: 5929616 (1999-07-01), Perraud et al.
patent: 6011666 (2000-01-01), Wakamatsu
patent: 6061306 (2000-05-01), Buchheim
patent: 6084387 (2000-07-01), Kaneko et al.
patent: 6184746 (2001-02-01), Crowley
patent: 6188212 (2001-02-01), Larson et al.
patent: 6194887 (2001-02-01), Tsukada
patent: 0 982 732 (2000-03-01), None
patent: 0 999 549 (2000-05-01), None
patent: 10028053 (1998-01-01), None
patent: PCT/US99/05734 (1999-09-01), None
U.S. application No. 09/643,819, Aram, filed Aug. 22, 2000.
U.S. application No. 09/654,392, Aram, filed Sep. 1, 2000.
U.S. application No. 09/648,770, Aram et al., filed Aug. 28, 2000.
U.S. application No. 09/648,464, Aram, filed Aug. 28, 2000.
Quantum Online / Inside Hard Disk Drives, “Part 2—A Closer Look at Hard Disk Drives”; “Chapter 3—Inside Hard Disk Drives—How They Work”, Jun. 7, 2000.
Quantum Online / Recent Technological Developments, “Chapter 4—The Impact of Leading-Edge Technology on Mass Storage”, Jun. 7, 2000.
Curtis Settles, “DSP-augmented CPU cores promise performance boost for ultra-compact drives”, Data Storage, May 2000, pp. 35-38.
Stephen H. Lewis, “Optimizing the Stage Resolution in Pipelined Multistage, Analog-to-Digital Converters for Video-Rate Applications”, IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, vol. 30, No. 8, Aug. 1992, pp. 516-523.
Stephen H. Lewis, et al., “A 10-b 20-Msample/s Analog-to-Digital Converter”, IEEE Journal of Solid-State Circuits, vol. 27, No. 3, Mar. 1992, pp. 351-358.
Stephen H. Lewis and Paul R. Gray, “A Pipelined 5-Msample/s 9-bit Analog-to-Digital C

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