High-speed reduced-output-swing self-biased...

Details High-speed reduced-output-swing self-biased... High-speed reduced-output-swing self-biased...

2007-03-20

2009-10-06

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S050000

Reexamination Certificate

active

07598777

ABSTRACT:
A CMOS comparator having a high-speed reduced-output-swing is provided. The high-speed reduced-output-swing comparator may have a fully complementary CMOS design, be self-biased, and have a rail-to-rail input common-mode range. The self-biasing scheme yields a robust comparator with a low sensitivity to temperature, processing variations, supply-voltage variations, and common-mode input voltages. The fully-complementary design leads to a physically small device with low power consumption. The rail-to-rail input common-mode range leads to a versatile comparator which may take a wide range of inputs. The high-speed reduced-output-swing allows for a quick output response to changes in the input.

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Bazes, M., “Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers”, IEEE Journal of Solid-State Circuits, vol. 26, No. 2, pp. 165-168, Feb. 1991.
Luo, L., et al., “3 Gb/s AC Coupled Chip-to-Chip Communication Using a Low Swing Pulse Receover”, IEEE Journal of Solid-State Circuits, vol. 41, No. 1, pp. 387-396, Jan. 2006.

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