High speed reception of encoded data utilizing dual phase resync

Details High speed reception of encoded data utilizing dual phase resync High speed reception of encoded data utilizing dual phase resync

1988-10-03

1990-03-27

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

328 72, 375 87, H04L 702

Patent

active

049127306

ABSTRACT:
A mechanism for recovering respective binary states of an input data signal in synchronism with transitions of the input data signal carries out the following sequence of steps. First, the binary state of the input data signal is sampled in accordance with consecutively occurring transitions of a high speed clock signal, the repetition frequency of which is at least three times the data transition rate. Upon the occurrence of a difference in binary state of successive samples of the input data signal at consecutive transitions of the clock signal, a signal representative of such a change is generated. In response to this change of state or transition-representative signal, the binary state of a delayed version of the input data signal, at a time whereat the input data signal is stable, is sampled. In order to reliably monitor the state of the communication link over which the data is transmitted, the binary state of the input data signal is periodically sampled. In addition, to prevent anomalies or `glitches` in the input data signal from erroneously being detected as data transitions, once the binary state of the input data signal is sampled, any further sampling is prevented for a prescribed period of time subsequent to that sampling, thereby permitting the data to stabilize.

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