High-speed real-time Reed-Solomon decoder

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G06F 1110

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048736880

ABSTRACT:
A Galois Field error correction decoder is described which can correct an error in a received polynomial. The apparatus includes means for generating a plurality of syndrome polynomials. A magnitude polynomial and a location polynomial having a first derivative are calculated from the syndrome polynomials utilizing Euclid's Algorithm. The module utilizing Euclid's Algorithm includes a general Galois Field multiplier having combinational logic circuits. The magnitude polynomial is divided by the first derivative of said location polynomial to form a quotient. Preferrably the division includes finding the inverse of the first derivative and multiplying the inverse by the magnitude polynomial. The error is corrected by exclusive ORing the quotient with the received polynomial.

REFERENCES:
patent: 4162480 (1979-07-01), Berlekamp
patent: 4413339 (1983-11-01), Riggle et al.
patent: 4434487 (1984-02-01), Rubinson et al.
patent: 4564945 (1986-01-01), Glover et al.
Berlekamp, Algebraic Coding Theory, McGraw-Hill Book Co., 1968, pp. 21-30.
"VLSI Reed Solomon Decoder Design" by Gary K. Maki, Patrick A. Owsley, Kelley B, Cameron and Jack Venbrux, published in Communications-Computers: Teamed for the '90's, Conference Record vol. 3 of 3, 1986 IEEE Military Communications Conference.
"Error-Correction Coding for Digital Communications" by George C. Clark, Jr. and J. Bibb Cain, pp. 195-201, published by Plenum Press, New York, First Printing Jun. 1981.

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