High-speed rail-to-rail comparator

Details High-speed rail-to-rail comparator High-speed rail-to-rail comparator

1999-10-28

2001-01-30

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S053000

Reexamination Certificate

active

06181169

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial No. 88113713, filed Aug. 11,1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to a comparator, and is more particularly related to a high-speed rail-to-rail comparator.
2. Description of Related Art
Reference is made to
FIG. 1A
, which shows a circuit of a conventional analog comparator. The comparator
5
includes two p-type metal oxide semiconductor (PMOS) transistors and two n-type metal oxide semiconductor (NMOS) transistors. As shown in
FIG. 1
A, a PMOS transistor
10
and a PMOS
20
are used for active loads. The comparator
5
is coupled to a reference signal Vref (Vss<Vref<Vcc) through a gate terminal of a NMOS transistor
30
, an input signal Vin through a NMOS transistor
40
and an output signal Vout through a drain terminal of the NMOS transistor
40
. The comparator
5
is also coupled to a fixed current source Is.
When the voltage level of the input signal Vin is larger than the Vref, the NMOS transistor
30
is closed and the NMOS transistor
40
is opened, and then the voltage level of the output signal Vout is very close to Vss. When the voltage level of the input signal Vin is smaller than Vref, the NMOS transistor
30
is opened and the NMOS transistor
40
is closed, and then the voltage level of the output signal Vout is also very close to Vcc.
The voltage level of the input signal Vin of the conventional comparator
5
is limited to a value between Vss and Vcc. If the voltage level of the input signal Vin is Vcc, the output signal Vout is very close to Vss; when the input signal Vin is rapidly changed to Vss, Vout is raised from a voltage level close to Vss and is raised to Vcc. By a similar manner, when the input signal Vin is rapidly changed from Vss to Vcc, Vout is decreased from a voltage level close to Vcc and is changed to Vss. A schematic diagram of a curve for Vin-Vout is shown in FIG.
1
B.
The swing range of the input signal Vin in the conventional comparator
5
is rail-to-rail, which is a voltage from Vcc to Vss or from Vss to Vcc. The swing range of the output signal Vout is larger in the conventional comparator. Therefore, a longer time is necessary in response to output a comparison result, which is a drawback for the comparator when used in a high-speed circuit.
Reference is made to
FIG. 2A
, which shows a conventional comparator
55
manifesting a phenomenon of magnetic hysteresis. The comparator
55
includes four PMOS transistors and two NMOS transistors. The PMOS transistors
52
and
54
are used as a active load
50
. The PMOS transistors
62
and
64
are used as another active load
60
. The comparator
55
is coupled to a reference signal Vref (Vss<Vref<Vcc) through a gate terminal of a NMOS transistor
70
, an input signal Vin through a NMOS transistor
80
and an output signal Vout through a drain terminal of the NMOS transistor
80
. The comparator
55
is also coupled to a fixed current source Is.
In the circuit of the comparator
55
, when the device parameter K
54
of the PMOS transistor
54
(device parameter
K
=
1
2
⁢
 
⁢
μ
n
⁢
C
OX
⁡
(
W
L
)
) is larger than the device parameter K
52
of the PMOS transistor
52
, and the device parameter K
64
of the PMOS transistor
64
is larger than the device parameter K
62
of the PMOS transistor
62
, as well, the phenomenon of magnetic hysteresis occurs in the comparator.
Reference is made to
FIG. 2B
, which shows a schematic diagram of a curve for Vin-Vout in a comparator manifesting a phenomenon of magnetic hysteresis. The comparator has two reference voltages V
+
ref and V
−
ref. When the voltage level of the input signal is larger than the reference voltages V
+
ref, the voltage level of the output signal is decreased from about Vcc to about Vss. When the voltage level of the input signal is smaller than the reference voltages V
−
ref, the voltage level of the output signal is increased from about Vss to about Vcc. The swing range of the output signal of the comparator with the phenomenon of magnetic hysteresis is very large; therefore, a longer time is required to respond and to output an accurate result. This longer time is also a draw-back for the comparator when used in a high-speed circuit.
SUMMARY OF THE INVENTION
The invention provides a high-speed rail-to-rail comparator, in which a voltage-dropped component is employed between connection of the output terminal and the active loads of the comparator. By employing the voltage-dropped component, a voltage level of the output terminal of the comparator can be easily controlled at a required level.
The invention provides a high-speed rail-to-rail comparator, in which a voltage-dropped component is employed between connection of the output terminal and the common source terminal of the comparator. By employing the voltage-dropped component, a swing range of the output voltage of the comparator can be controlled and limited, by which the transferring speed of the output of the comparator can be easily faster than that in the conventional comparator. This invention is therefore suitable for application in a high-speed circuit.
In accordance with the foregoing and other objectives of the present invention, a high-speed rail-to-rail comparator is provided. The comparator comprises two PMOS transistors, two NMOS transistors, a current source and two voltage-dropped components. A first PMOS transistor is provided. A source terminal of the PMOS transistor is coupled to a first voltage source, and a gate terminal and a drain terminal of the first PMOS transistor are coupled to each other. A second PMOS transistor is also provided. A source terminal of the second PMOS transistor is coupled to the first voltage source, and a gate terminal of the second PMOS transistor is coupled to the gate terminal of the first PMOS transistor. A first NMOS transistor has a drain terminal coupled to the drain terminal of the first PMOS transistor and a gate terminal coupled to a reference signal. A second NMOS transistor has a drain terminal coupled to the drain terminal of the second PMOS transistor and coupled to an output terminal, while a gate terminal of the second NMOS transistor is coupled to an input terminal and a source terminal of the second NMOS transistor is coupled to a source terminal of the first NMOS transistor. A current source has a current source that is coupled to the source terminal of the first NMOS transistor, while an output terminal of the current source is coupled to a second voltage source and the voltage provided by the first voltage source is larger than the voltage provided by the second voltage source. A first voltage-dropped component has a positive terminal of the first voltage-dropped component coupled to the gate terminal of the second PMOS transistor and a negative terminal of the first voltage-dropped component is coupled to the drain terminal of the second NMOS transistor. A second voltage-dropped component has a positive terminal coupled to the drain terminal of the second NMOS transistor and a negative terminal coupled to the source terminal of the second NMOS transistor.
In accordance with the foregoing and other objectives of the present invention, a high-speed rail-to-rail comparator is provided. The comparator comprises four PMOS transistors, four NMOS transistors, a current source and four voltage-dropped components. A first PMOS transistor has a source terminal coupled to a first voltage source. A second PMOS transistor has a source terminal coupled to the first voltage source, and a gate terminal of the PMOS transistor is coupled to a gate terminal of the first PMOS transistor. A third PMOS transistor has a source terminal coupled to the first voltage source, and a drain terminal of the third PMOS transistor is coupled to a drain terminal of the second PMOS transistor. A fourth PMOS transistor has a source terminal coupled to the first voltage source and a gate terminal coupled to a gate terminal

Affiliated with

Also associated with

Rating

High-speed rail-to-rail comparator does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High-speed rail-to-rail comparator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-speed rail-to-rail comparator will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2439657