High speed R-S latch

Details High speed R-S latch High speed R-S latch

1988-04-04

1989-04-25

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307491, 307494, H03K 3356

Patent

active

048251003

ABSTRACT:
According to the present invention, an R-S latch includes an input stage, a double gate latch stage, and an output stage. The input stage includes a pair of source couplet FETs, a pair of active loads, and a biasing current source. The output of the input stage is coupled to both the latch stage and the output stage, which contains a pair of source follower FETs. The latch stage includes a pair of source coupled double gate FETs. The latch stage provides the switching or latching mechanism which prevents the outputs from changing logic stage until an appropriate set or reset pulse is received. However, one pair of the gates in the latch stage are coupled to an inverted set and reset input. This pair of additional gates enables the Q and Q output to switch symmetrically, thus preventing delay between the Q and Q output.

REFERENCES:
patent: 4654547 (1987-03-01), Shaver
W. B. Chin et al., "Cmplementary MOS Set/Reset Latch" IBM Tech. Discl. Bul. vol. 15, No. 9, Feb. 1973, p. 2918.

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