High speed PWM without linearity compromise at extreme duty cycl

Details High speed PWM without linearity compromise at extreme duty cycl High speed PWM without linearity compromise at extreme duty cycl

1993-02-01

1995-01-03

Chin, Stephen

Pulse or digital communications

Repeaters

Testing

375 76, 370 9, 327172, 327175, H03K 908

Patent

active

053793218

ABSTRACT:
A circuit for reducing the amount of instability in a pulse width modualtion circuit by providing a minimum amount of overdrive after the crossover point between a ramp and a voltage threshold level, and a constant amount of discharge time between the end on one ramp and the beginning of the next. Also, a feedback loop is privided to increase or decrease the slope to compensate for a decreasing or increasing amount of time between clock pulses, to maintain the duty cycle of the output when the clock frequency varies.

REFERENCES:
patent: 3840890 (1974-10-01), Sunderland
patent: 4333108 (1982-06-01), Quan et al.
patent: 4669089 (1987-05-01), Gahagan et al.
patent: 5198785 (1993-03-01), Jordan
patent: 5208559 (1993-05-01), Jordan

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