High-speed programmable state counter

Details High-speed programmable state counter High-speed programmable state counter

1992-01-06

1993-04-27

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

377 39, 3072722, 307455, H03K 2340

Patent

active

052065472

ABSTRACT:
A programmable state counter generates an output signal when a predetermined count sequence matches a programmed input data pattern. A synchronous maximal length shift counter generates 2.sup.N -1 unique output states as a predetermined count sequence. A string of first flipflops receive the programmed input data pattern at first data input and the predetermined count sequence at second data inputs. The first and second data inputs of first flipflops are combined as a logical exclusive-NOR operation. A second flipflop has a first data input wired-OR'ed to inverted outputs of a first portion of the first flipflops, and a second data input wired-OR'ed to the inverted outputs of a second portion of the first flipflops. The first and second data inputs of the second flipflop are combined as a logical OR operation for providing the output signal of the programmable state counter.

REFERENCES:
patent: 3720910 (1973-03-01), McLaughlin et al.
patent: 4608706 (1986-08-01), Chang et al.
patent: 4628216 (1986-12-01), Mazumder
patent: 5155383 (1992-10-01), Barbera

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