High speed programmable read only memory device having a high in

Details High speed programmable read only memory device having a high in High speed programmable read only memory device having a high in

1989-10-13

1990-10-09

Clawson Jr., Joseph E.

Static information storage and retrieval

Read only systems

Fusible

36523006, G11C 1700

Patent

active

049624784

ABSTRACT:
A programmable read only memory device according to the present invention has a plurality of memory cells each formed by, for example, a bipolar transistor or a series combination of a fuse element or a diode and associated with an addressing facility which has a plurality of row selector units coupled to word lines, respectively, and each of the row selector units has a decoder stage accompanied with an amplifying bipolar transistor and an output bipolar transistor coupled to the amplifying bipolar transistor for discharging a large amount of a write in current and a small amount of a read out current on the associated word line to the ground, wherein a diode is coupled between the associated word line and the amplifying bipolar transistor for supplying a part of the write in current through the amplifying bipolar transistor to the base node of the output bipolar transistor, so that the output bipolar transistor is decreased in transistor size by virtue of sharing the write in current between the collector node and the base node of the output bipolar transistor.

REFERENCES:
patent: 4174541 (1979-11-01), Schmitz
patent: 4385368 (1983-05-01), Principi et al.
patent: 4424582 (1984-01-01), Fukushima et al.
patent: 4656606 (1987-04-01), Ohno et al.
patent: 4706222 (1987-11-01), Kwiatkowski et al.

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