High speed programmable prescaler

Electrical pulse counters – pulse dividers – or shift registers: c – Starting – stopping – presetting or resetting the counter – Counter chains with a radix or base other than the number...

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377 47, 377 52, 377119, H03K 2136, H03K 2326

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045758670

ABSTRACT:
A high speed programmable prescaler has an input divider that divides an input stream of clock pulses by either 2 or upon command by 3. Connected to the input divider is a plurality of dividers that are electrically cascaded together from a first member to last member with each member of the plurality of dividers being capable of dividing the clock pulses applied to it by either 2 or upon command by 3. A prescaler selects either 2 or 3 for dividing the input stream of clock pulses so that number of clock pulses necessary to obtain an output pulse can be represented by the equation of 2.sup.N +M where N is the number of members of the plurality of dividers and M is the control number having a range of 0 to 2.sup.N -1.
The critical path delays are minimized by using a flip-flop in the input divider to divide by 2 and then on command shifting the output of the flip-flop by 180.degree. to obtain the divide by 3 function.

REFERENCES:
patent: 3493872 (1970-02-01), Sepe
patent: 3811092 (1974-05-01), Charbonnier
patent: 4016495 (1977-04-01), Machanian
patent: 4264863 (1981-04-01), Kojima
patent: 4331926 (1982-05-01), Minakuchi
Paphitis, IEEE Trans. on Instrumentation and Measurement, vol. 1M-26, No. 4, pp. 396-402; 12/1977.
Cavalli-Sforza et al, Nuclear Instruments and Methods, I3I, No. 3, Dec. 28, 1975, pp. 575-578; North-Holland Publishing Co.

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