Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Reexamination Certificate
2002-08-06
2004-07-06
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
C377S048000
Reexamination Certificate
active
06760397
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of electronic devices, and in particular to a high-speed programmable frequency-divider, or multimodulus prescaler, that can be loaded with a new divisor without disturbing the counting process.
2. Description of Related Art
FIG. 1A
illustrates a conventional programmable frequency-divider
100
, or multimodulus prescaler, based on the principles disclosed in “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-&mgr;m CMOS Technology” by Cicero S. Vaucher et al. in the IEEE Journal of Solid-State Circuits, Vol. 35, No. 7, July 2000, and incorporated by reference herein. The frequency-divider
100
, divides a frequency of an input signal, In, by a programmed amount. Each counter-stage
110
is a programmable divide-by-2-or-3 counter.
Ignoring for the moment the combinatorial logic
118
that couples the last four stages J
1
, J
2
, J
3
, and J-Last of the divider
100
, if each of the stages are configured to divide by 2, the divider
100
will divide the input frequency by 2
n
, where n equals the number of counter stages
110
; in this example n equals 8. Each of the counter-stages
110
is configured to be enabled to divide by 3 once per dividing cycle; the input Min of each stage
110
provides this once-per-dividing-cycle enabling signal. When enabled, if the program input pg<x> of stage x is a logic-one, stage x divides by 3; if the input pg<x> of stage x is a logic-zero, stage x divides by 2. Division by 3 adds one extra cycle at the duration period of the particular stage. That is, for example, if the pg<3> input is a logic-one, the third stage will divide by 3 once per division cycle, adding an extra 2
3
clock cycles to the duration of the division cycle; if pg<5> is logic-one, the fifth stage will add an extra 2
5
clock cycles to the duration of the division cycle. The period of the division cycle of a divider
100
of length n, therefore, can be expressed as:
T
out=2
n
T
in+
pg<n
−1>2
n−1
T
in+ . . . +
pg
<1>2
1
T
in+
pg
<0
>T
in, (1)
where Tin corresponds to the input clock cycle period. Thus, absent the combinatorial logic
118
that couples the last four stages J
1
, J
2
, J
3
, JLast, the divisor can range between 2
n
and 2
n+1
−1, which, in this case equates to a range of 256 through 511.
The combinatorial logic
118
that couples the last four stages J
1
, J
2
, J
3
, and J-Last provides a reduction in the effective length, n′, of the divider
100
, by effectively ignoring all of the upper stages beyond the most significant bit of the current programmed divisor, to produce an output period of:
T
out=
pg<n
>2
n
T
in+
pg<n
−1>2
n−1
T
in+ . . . +
pg
<1>2
1
T
in+
pg
<0
>T
in, (2)
provided that the programmed divisor's most significant bit is at least at the J
1
, J
2
, J
3
, or J-Last position. That is, using the illustrated combinatorial logic to couple the upper k counter-stages
110
, the divisor can range between 2
n+1−k
and 2
n+1
−1. In the example, with n=8 and k=4, the divisor can range between 2
5
and 2
9
−1, or, 32 to 511.
Equation (2) can be expressed in terms of a divisor output frequency Fout as:
Fout
=
Fin
pg
⟨
n
⟩
2
″
+
pg
⟨
n
-
1
⟩
2
n
-
1
+
…
+
pg
⟨
1
⟩
2
′
+
pg
⟨
0
⟩
,
(
3
)
where Fin corresponds to the frequency of the input signal. Because the Min signal to each of the counter-stages F, G, H, and I occurs once per division cycle, any of these signals may be used as the output signal having the above defined output frequency. Typically, the Min signal to the I stage is used as the output signal, because it has the longest pulse duration, and therefore the lowest high-frequency component, of the stages F, G, H, and I.
As the title of the referenced article indicates, the structure of
FIG. 1A
is selected for modularity. Each of the counter-stages
100
of
FIG. 1A
are identical, and thus a redesign of the divider
100
as design rules and feature sizes change can be easily accommodated by modifying the common design of the stage
110
.
For ease of subsequent reference,
FIG. 1B
illustrates the same programmable frequency-divider
100
, having a different structural partitioning than that illustrated in FIG.
1
A. In this embodiment, there are three different counter-stage modules
120
,
130
, and
140
. Each of the modules
120
include the corresponding counter stage F, G, H, I and J
110
and associated D-flip-flop
115
of
FIG. 1A
that holds the program value pg<x>, and is illustrated in FIG.
3
. Each of the modules
130
includes the corresponding counter-stage J
2
, J
3
110
, D-flip-flop
115
, and combinatorial logic
118
, and is illustrated in FIG.
10
. The module
140
includes the corresponding counter stage J-Last
110
, the D-flip-flops
115
and
116
, and the combinatorial logic
118
; the module
140
corresponds to the addition of D-flip-flop
116
to the module
130
that is illustrated in
FIG. 10
to provide the input signal (Zin) to the combinatorial logic
118
.
As discussed in the referenced article, a common application of the programmable frequency-divider
100
is as a frequency synthesizer for demodulating high-frequency signals, such as radio signals, including radio signals at substantially different frequency bands. In such an application, reloading or reprogramming a new divisor value corresponds to a change-of-channel to a new receiver or transmitter frequency. Because the reprogramming corresponds to a discontinuous change, there is no need to assure that the current progression of counting is not disturbed when the new divisor values pg<x> are programmed. In other applications, however, such as when used as the counting element in a fractional divider, wherein the programmed divisor repeatedly changes from a value of N to a value of N+1, then back to N, it is essential that the running count not be disturbed during each reprogramming of the divider. That is, the, divider
100
must divide by either the original divisor or the new divisor, only. If the new divisor is loaded while one or more of the stages
110
of the divider
100
is sensitive to the programmed divisor value, i.e. enabled to divide-by-three or divide-by-two, depending upon the programmed divisor value, the effective division may be a value that is neither the original divisor nor the new divisor value, because part of the count in the division cycle will be based on the original divisor, and the remainder based on the new divisor.
FIG. 2
illustrates a typical timing diagram of the divide-by-3-enable signals, MinF-MinJLast, in a conventional frequency-divider
100
. Also illustrated are select outputs QJ
2
, QJ
3
, and QJLast, for timing reference. As noted above, each stage x is enabled to divide by either two or three, depending upon the stage's programmed value pg<x>, only when the incoming enabling signal, MinX, is active. In the illustrated timing diagram, the enabling signals MinF-MinJLast are active-high. A safe-load time period
210
is illustrated in
FIG. 2
as commencing after all of the enabling signals MinF-MinJLast enter the inactive (low) state, at
220
. Generally, the safe-load period extends at least for the duration of all the enabling signals remaining in the inactive state, at
230
. If the details of the embodiment of the stages
110
are known, the extent of the safe-load period can be more precisely determined. In the conventional embodiment of a frequency-divider
100
with a counter-stage
110
, for example, the safe period
210
ends when one of the enabling signals goes inactive while others remain active, or have not yet become
Gaithke Rainer
Wu Hongbing
Koninklijke Philips Electronics , N.V.
Wambach Margaret R.
Waxcer Aaron
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