Electrical pulse counters – pulse dividers – or shift registers: c – Starting – stopping – presetting or resetting the counter – Counter chains with a radix or base other than the number...
Patent
1986-09-29
1988-04-26
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Starting, stopping, presetting or resetting the counter
Counter chains with a radix or base other than the number...
377 52, 377111, H03K 2366
Patent
active
047410043
ABSTRACT:
A programmable divide-by-N counter employs a plurality of speed enhancement techniques to provide an overall operational speed corresponding to the speed at which a single-clocked flip-flop is capable of being toggled. The counter configuration provides flexibility in selecting the value of N, the programmable divisor, as well as the possibility of increasing the length the counting chain without producing a reduction in overall operational speed. The speed enhancement techniques are primarily located in the reset logic portion of the counter. A key aspect utilized through-out the overall circuit is that critical signal propagation paths in terms of speed of operation present no more than four gate delay intervals in total response time.
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Article from IEEE Journal of Solid-State Circuits, vol. SC-20, No. 6, Dec. '85, by Rocchi et al., pp. 1194 to 1199.
Heyman John S.
Microwave Semiconductor Corporation
Moran John F.
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