High speed programmable counter

Details High speed programmable counter High speed programmable counter

1999-05-18

2001-05-01

Olms, Douglas (Department: 2661)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

Reexamination Certificate

active

06226295

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a programmable counter and more specifically to a counter with programmable start and stop counts.
REFERENCE TO RELATED APPLICATIONS
A United States patent entitled “Self-Queuing Serial Output Port” filed Sep. 28, 1995, now issued as U.S. Pat. No. 5,680,425 is assigned to the same assignee as the present application and is incorporated herein by reference.
BACKGROUND OF THE INVENTION
Asynchronous Transfer Mode (ATM) communication switches have multiple output ports to perform high speed switching of multibyte cells of data. The switches are generally formed with a shared memory for buffering multiple cells of data, and several ports coupled to the memory for transferring data between the memory and busses or channels attached to the switch. Counters are used to provide a running total of how many bytes or nibbles (half bytes) of a cell have been transferred. In addition, there are countless uses for counters deep inside semiconductor chips used for executing instructions in computers and assisting with basic electronic circuit functions. Many of the counters are specifically designed for each intended purpose. This leads to extra effort in modifying each design to count to a specific number, and provide functions to start stop, continue and reset the count. When counters are used to help implement communication protocols such as ATM, there may be different lengths of cells for which each byte of the message must be counted. A different set of counters may be needed for each message length, increasing design cost and complexity. There is a need for a flexible counter than can handle different length cells without the need for reprogramming.
SUMMARY OF THE INVENTION
A digital counter allows the provision of start and stop addresses in order to allow it to be configurable to any length, and to start and stop at desired positions in a cell of data. This provides a robust design that can easily be utilized in a larger circuit with little or no modification, minimizing design cost and complexity. In one embodiment, the counter rolls over to 0 after reaching a maximum value of 111 (112 cycles). The counter counts to 111 and then goes back to 0, continuing to count until it reaches an indicated stop count. At that point, it proceeds to the start count and continues counting. In this manner, the start count value may actually be higher than the stop count because the counter will just roll over and being counting at 0 until it reached the stop count.
In a further embodiment, the counter is used to identify the length of message packets or cells being processed in accordance with a communication protocol such as ATM (asynchronous transfer mode). The counter start and stop addresses are variably set in accordance with the number of bytes of data in each cell which is being transferred to and from memory and a bus or channel. With a roll over value of 112, and data being transferred in nibbles of four bits, an entire 56 byte ATM cell may be counted without resetting the counter. Cells of shorter length may also be counted without having to intervene to reset the counter, or providing a separate counter for each cell length.


REFERENCES:
patent: 3878510 (1975-04-01), Smith
patent: 5373542 (1994-12-01), Sunouchi
patent: 5825766 (1998-10-01), Kobayashi et al.

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