High speed processing unit

Details High speed processing unit High speed processing unit

1992-01-27

1994-04-26

Mai, Tan V.

Boots, shoes, and leggings

G06F 738

Patent

active

053073002

ABSTRACT:
A processing unit has a first data bus and a second data bus that receive first and second data from, respectively, first and second registers in a register file. An arithmetic-logic unit performs arithmetic and logic operations on the first and second data to produce third data, which it places on a third data bus. A selection circuit coupled to the first and third data buses selects either the first or third data for input to a third register in the register file, and either the first or third data for input to a fourth register in the register file. The first, second, third, and fourth registers are selected by a control circuit.

REFERENCES:
patent: 4773006 (1988-09-01), Kinoshita et al.
patent: 4922418 (1990-05-01), Dolecek
patent: 4949292 (1990-08-01), Hashino et al.
patent: 4967343 (1990-10-01), Ngai et al.
patent: 5073970 (1991-12-01), Aoyama et al.
Glenford J. Myers and David L. Budde, The 80960 Microprocessor Architecture, pp. 195-199 of Japanese translation published by Maruzen.

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