Electrical pulse counters – pulse dividers – or shift registers: c – Starting – stopping – presetting or resetting the counter
Patent
1983-01-28
1985-04-16
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Starting, stopping, presetting or resetting the counter
377117, 377121, 377105, 307450, H03K 19017, H03K 2136, H03K 2322
Patent
active
045120307
ABSTRACT:
A high speed countdown counter (FIG. 7) capable of operation at up to 10 MHz is provided which comprises a number of stages each comprising a flip flop (134, 136; 144, 146; etc.), a preset data input (IN1, IN2, etc.), a carry input (N11, N10, etc.), a data output (N5, N4, etc.), and a carry output.
Dynamic Depletion Mode (DDM) transistors (129, 139, etc.) are employed to reduce charging time at inter-stage nodes and thereby improve speed, while minimizing circuit size and power requirements.
A look-ahead feature enables early detection of an "all zero minus one" count and enables the presetting of data into the counter simultaneously with the generation of a "carry out" signal from the counter. Various internal counter control signals are delayed by couplers driven by a two-phase non-overlapping clock, in order to allow for signal propagation time through the corresponding circuit elements.
REFERENCES:
patent: 3930169 (1975-12-01), Kuhn
patent: 4002926 (1977-01-01), Moyer
patent: 4330751 (1982-05-01), Swain
patent: 4435658 (1984-03-01), Murray et al.
patent: 4469962 (1984-09-01), Snyder
Heyman John S.
Motorola Inc.
Nielsen Walter W.
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