High-speed predecoding address counter circuit

Details High-speed predecoding address counter circuit High-speed predecoding address counter circuit

1996-12-27

1998-08-25

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Applications

Including memory

377111, 377116, 36523006, 365236, H03K 2102

Patent

active

057990530

ABSTRACT:
A high-speed predecoding address counter circuit comprising at least three tetrad counters connected in series, each for inputting an external 4-bit address decoding signal in response to a set signal and cyclically shifting a logic signal with a specific logic value at its four output terminals in response to a clock signal, a first clock switching unit responsive to a logical value of a most significant bit of an output signal from a lowest-order one of the at least three tetrad counters, for transferring the clock signal to a higher-order one of at least three tetrad counters, at least one logic unit for detecting whether both most significant bits of output signals from at least two lower-order ones of the at least three tetrad counters have the specific logic value, and at least one second clock switching unit connected between at least one logic unit and at least one of the at least three tetrad counters other than the at least two lower-order tetrad counters, for switching the clock signal to the at least one tetrad counter in response to an output signal from at least one logic unit. According to the present invention, because of a minimized propagation delay time, the address counter circuit generates internal address signals with a high-speed response characteristic with respect to the clock signal.

REFERENCES:
patent: 4503525 (1985-03-01), Malik et al.
patent: 5117388 (1992-05-01), Nakano et al.
patent: 5668772 (1997-09-01), Hotta
patent: 5706233 (1998-01-01), Ooishi

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