High speed post-programming net verification method

Details High speed post-programming net verification method High speed post-programming net verification method

1995-08-04

1997-04-01

Karlsen, Ernest F.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324538, G01R 3102

Patent

active

056170211

ABSTRACT:
A method and structure for verifying interconnect structure of an FPGA device after programming. In a preferred embodiment, after programming, a single wire segment on each net of a layout is pulled down to a low reference voltage. Voltage levels on all wire segments of the device are then captured and shifted out of the device for comparison to the expected values. Low voltage levels on segments expected to remain high reveal short circuit flaws. High voltage levels on segments expected to remain low reveal open circuit flaws.

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