High speed post-programming net packing method

Details High speed post-programming net packing method High speed post-programming net packing method

1995-08-04

1997-09-30

Karlsen, Ernest F.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

371 225, G01R 3128

Patent

active

056729669

ABSTRACT:
A method and structure for verifying interconnect structure of an FPGA device after programming. In a preferred embodiment, after programming, a single wire segment on each net of a layout is pulled down to a low reference voltage. Voltage levels on all wire segments of the device are then captured and shifted out of the device for comparison to the expected values. Low voltage levels on segments expected to remain high reveal short circuit flaws. High voltage levels on segments expected to remain low reveal open circuit flaws. The test is conducted simultaneously on a group of packed nets, wherein each group comprises a number of disjoint nets separated from one another by at least two MicroVia.TM. interconnects. A preferred packing method minimizes the number of net groups on a device for maximum test efficiency.

REFERENCES:
patent: 4241307 (1980-12-01), Hong
patent: 4670708 (1987-06-01), Bosnyak et al.
patent: 5083083 (1992-01-01), El-Ayat et al.
patent: 5291079 (1994-03-01), Goetting
patent: 5319254 (1994-06-01), Goetting
patent: 5430678 (1995-07-01), Tomita et al.

Affiliated with

Also associated with

Rating

High speed post-programming net packing method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed post-programming net packing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed post-programming net packing method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2259576