Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1998-08-11
2002-04-30
Hiteshew, Felisa (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C156S345420, C451S288000
Reexamination Certificate
active
06380086
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a high-speed wafer planarizing machine for use in chemical-mechanical planarization of semiconductor wafers.
BACKGROUND OF THE INVENTION
Chemical-mechanical planarization (“CMP”) processes are used to remove materials from the surface layer of a wafer in the production of ultra-high density integrated circuits. In a typical CMP process, a wafer is pressed against a slurry on a polishing pad under controlled chemical, pressure, velocity and temperature conditions. Current polishing pads have diameters of approximately two feet, and they are rotated on a platen at approximately 20 to 40 rpm. Wafers typically have diameters of 6 to 8 inches, and they are simultaneously rotated at approximately 10 to 30 rpm and translated across the polishing pad. The slurry solution contains small, abrasive particles that mechanically remove material from the surface layer of the wafer as the wafer is moved over the pad.
After a wafer is planarized, it is removed from the polishing pad and rinsed with deionized water to remove residual particles on the surface of the wafer. Wafers are typically re-planarized a second time to obtain a uniformly planar surface at a desired end point, and then they are removed from the planarizing machine and re-rinsed with deionized water.
CMP processes must consistently and accurately create a uniform, planar surface on the wafer at a desired endpoint. Many microelectronic devices are typically fabricated on a single wafer by depositing layers of various materials on the wafer, and manipulating the wafer and the other layers of material with photolithographic, etching, and doping processes. In order to manufacture ultra-high density integrated circuits, CMP processes must produce a highly planar surface so that the geometries of the component parts of the circuits may be accurately positioned across the full surface of the wafer. Integrated circuits are generally patterned on a wafer by optically or electromagnetically focusing a circuit pattern on the surface of the water. If the surface of the wafer is not highly planar, the circuit pattern may not be sufficiently focused in some areas, resulting in defective circuits. Therefore, it is important to accurately planarize a uniformly planar surface on the wafer.
One problem with current CMP planarizers is that they do not produce a wafer with a sufficiently uniform surface because the relative velocity between the wafer and the pad changes from the center of the wafer to its perimeter in proportion to the radial distance from the center of the wafer. The center-to-edge velocity profile generally causes the perimeter of the wafer to have a different temperature, and thus a different polishing rate, than the center of the wafer. Accordingly, it would be desirable to reduce or eliminate the center-to-edge velocity profile across the wafer.
In the competitive semiconductor industry, it is also highly desirable to maximize the throughput of CMP processes to produce accurate, planar surfaces as quickly as possible. The throughput of CMP processes is a function of several factors, including the rate at which the thickness of the wafer decreases as it is being planarized (“the polishing rate”), and the ability to perform the rinsing and planarizing steps quickly. A high polishing rate generally results in a greater throughput because it requires less time to planarize a wafer. Similarly, performing the planarizing and rinsing steps quickly reduces the overall time it takes to completely planarize a wafer. Thus, it would be desirable to maximize the polishing rate and minimize the time required to perform the planarizing and rinsing steps.
Another problem with current CMP processes is that the polishing rates are limited because the center-to-edge velocity profile across the wafer limits the maximum velocity between the wafer and polishing pad. As stated above, the polishing rate is a function of the relative velocity between the wafer and the pad. Rotating the wafer at higher speeds, however, only exacerbates the center-to-edge velocity profile across the surface of the wafer because the difference between the linear velocity at the perimeter of the wafer and the center of the wafer increases as the angular velocity of the wafer increases. Accordingly, it would be desirable to provide a wafer planarizer that increases the maximum velocity between the wafer and the pad without increasing the center-to-edge velocity profile across the wafer.
Still another problem of the current CMP processes is that the procedure of planarizing, rinsing, re-planarizing, and re-rinsing is time-consuming. In current CMP processes, the wafer is moved back and forth between the planarizing machine and a wafer rinser throughout the process. Each time the wafer is moved from the planarizer to the wafer rinser, an arm picks up the wafer and physically moves it over to the wafer rinser. The wafer planarizer is idle while the wafer is being rinsed, and the wafer rinser is idle while the wafer is being planarized. In current CMP processes, therefore, either the wafer planarizer or the wafer rinser is idle at any given time. Thus, it would be desirable to provide a more efficient wafer planarizer and wafer rinser.
SUMMARY OF THE INVENTION
The inventive high-speed planarizing machine has a platform that holds the wafer stationary during planarization, and a carrier positioned opposite the platform. The carrier rotates about an axis and is translated in a plane that is substantially parallel to the wafer. A polishing pad is attached to the carrier and positioned opposite the wafer. The carrier rotates and translates the polishing pad across the wafer while the wafer is held stationary.
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Robinson Karl M.
Stroupe Hugh
Chen Kin-Chan
Dorsey & Whitney LLP
Hiteshew Felisa
Micro)n Technology, Inc.
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