High speed pin driver integrated circuit architecture for commer

Details High speed pin driver integrated circuit architecture for commer High speed pin driver integrated circuit architecture for commer

1998-12-23

2000-12-05

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

327478, H03B 100

Patent

active

061572241

ABSTRACT:
An improved high speed PIN driver integrated circuit and architecture. The architecture of the PIN driver circuit does not rely on transistor clamping during normal operation in active mode, and does not require high reverse base-emitter breakdown voltage in inhibit mode or the active mode, which is in direct opposition to high speed performance at high PIN voltage excursions for CMOS, TTL, ECL level compatibility. In particular, the PIN driver circuit is always an active linear circuit and does always protects the reverse base-emitter voltage of any transistor and does not require wire-OR or clamp transistors. The architecture uses replica biasing to cancel the current of the PIN driver in the inhibit mode, which is a requirement for automatic test equipment where the leakage current produces at the PIN in the inhibit mode is not calibrated out. The replica biasing is implemented using a current mirror circuit, a summing device and a buffer circuit which generates the voltage replica in an active mode of the PIN driver circuit. The replica biasing scheme used in the present invention tracks over temperature and process, and provides for improved high speed circuitry without the need for calibration of leakage currents in the inhibit mode.

REFERENCES:
patent: 4251742 (1981-02-01), Beelitz
patent: 4800294 (1989-01-01), Taylor
patent: 5146159 (1992-09-01), Lau et al.
patent: 5179293 (1993-01-01), Hilton
patent: 5302859 (1994-04-01), Whitney
patent: 5357211 (1994-10-01), Bryson et al.
patent: 5377202 (1994-12-01), Lee et al.
patent: 5699001 (1997-12-01), Awaji et al.

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