High speed phase locked loop

Details High speed phase locked loop High speed phase locked loop

2005-09-06

2005-09-06

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

06940322

ABSTRACT:
A high speed CMOS phase locked loop (PLL) (10) includes a three-state phase detection circuit having a frequency phase detector (12) coupled to a charge pump (14) for monitoring the phase differences between a reference frequency signal and a divided output frequency signal. The PLL can further include a loop filter (16)coupled to the three-state phase detection circuit, a VCO (18) coupled to the output of the loop filter, a VCO buffer (22) coupled to the output of the VCO for providing an output frequency signal, and a dual modulus prescaler (28) having a synchronous counter (27and29) using feedback among D flip-flops (30and32) for generating the divided output frequency signal.

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