High-speed phase frequency detection module

Details High-speed phase frequency detection module High-speed phase frequency detection module

2002-01-15

2004-08-17

Choe, Henry (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S00100A, C327S156000, C375S374000

Reexamination Certificate

active

06778026

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of high frequency data transmission systems and, more specifically, to phase-lock-loops, synthesizers, and high-speed phase frequency detection devices.
BACKGROUND OF THE INVENTION
As wireless communication devices increase in number and complexity, there is an ever increasing need for wireless communication devices and systems that can function at very high frequencies. To this end, high-speed phase-frequency detection devices that can handle higher frequencies are needed.
Typically, phase-frequency detection devices are used in phase-lock-loops. A phase-lock-loop compares the phase and/or frequency of a generated clock signal (or more often a divided version of it) to that of a pure reference clock signal of known accurate frequency and adjusts the frequency and phase of the generated clock signal until it is “locked” in both frequency and phase to the reference clock signal. Thus, a clock signal of a high frequency that is a multiple of the reference frequency is established, which becomes the base for high-frequency wireless communication systems.
FIG. 1A
is an illustration of a typical phase-lock loop
100
. It includes a phase-frequency detector (“PFD”)
102
, a charge pump
104
, a voltage controlled oscillator (“VCO”)
106
, a loop filter
108
, and most often a divider
110
. The PFD
102
compares the phase and frequency of a reference clock signal (Reference Clock) to a feedback clock signal (Feedback Clock). The Feedback Clock signal is generated by the divider
110
, which divides down from the VCO
106
output (Output Clock). If the Feedback Clock and the Reference Clock are out of phase, the PFD
102
will generate corrective voltage signals (Vup or Vdown) to trigger the charge pump
104
to either source current into (Iup) or sink current from (Idown) the loop filter
108
, hence increase or decrease the control voltage (Vcntl) going into VCO
106
. The control voltage drives the frequency of the clock signal higher or lower, until the clock signal and the reference signal are matched in phase and frequency, or “locked.” When the loop locks, the charge pump
104
should stops sourcing or sinking current, thus leaving the control voltage relatively constant.
However, even when locked, the PFD
102
may experience jitter, or small noise error, in what is known as the “dead zone,” depicted in FIG.
1
B. Jitter as a result of dead zone occurs when the Feedback Clock signal varies slightly from the Reference Clock signal and very small phase differences develops (&Dgr;&phgr;). When the phase difference is slight enough, finite rise and fall times of the PFD pulse signals, caused by circuit-element capacitance, may not find enough time to reach a good logic high level, hence failing to turn on/off the charge pump current switches. This leads to random variation in the VCO
106
output, or jitter.
One solution to eliminate jitter in the dead zone is to generate overlapping reset pulses, with wide enough pulse widths, to turn on/off the charge pump switches, also shown in FIG.
1
B.
FIG. 1C
shows the input-output characteristic of the ideal PFD, PFD with dead zone, and PFD with a reset pulse. Generally, when overlapping reset pulses are too wide, more information of phase relationship is lost, which affects the performance of the phase-lock-loop system. Thus, the reset pulse has to remain narrow, compared to the period of the clock signals, to achieve good loop dynamics.
Many communication systems today are operated at very high frequencies, such as the 5.18 GHz to 5.805 GHz frequency spectrum used for the, 802.11a standard. Unfortunately, current phase-lock-loop devices, such as PFDs (see
FIG. 1D
) and charge pumps (see FIG.
1
E), are too slow and thus cannot create corrective pulses and control voltages for very high frequencies. In addition, current charge pumps, like the one shown in
FIG. 1E
, require complicated feedback and replica circuit to function properly. Such excessive circuitry add complexity to the circuit design and cause instability when used at high frequencies.
SUMMARY OF THE INVENTION
A high-speed phase-frequency detection module is described to function at very high frequencies and to produce very low jitter. In one embodiment, high-speed phase-frequency detection module includes a PFD with edge-triggered asynchronous-reset true-single-phase-clocking (“TSPC”) D flip-flops that have very short CLK to Q and Reset to Q time delays. In one embodiment, the high-speed phase-frequency detection module includes a charge pump, without replica or feedback, that can respond to the very narrow pulses from the PFD and produce output voltages with small ripple, thus leading to low VCO output jitter. Other features of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.


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PCT Search Report for PCT/US 03/00689, 4 pages, Oct. 8, 2003.
Hirad Samavali, Hamid R. Rateghm, Thomas H. Lee, ISSCC 2001/Session 13/Wireless LAN 13.7, 2001 IEEE International Solid-State Circuits Conference.

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