High-speed partitioned set associative cache memory

Details High-speed partitioned set associative cache memory High-speed partitioned set associative cache memory

1988-09-07

1990-07-31

Hecker, Stuart N.

Static information storage and retrieval

Associative memories

Ferroelectric cell

36518901, 36523006, 371 102, G11C 700, G11C 2900, G06F 1100

Patent

active

049455125

ABSTRACT:
A high-speed partitioned set associative cache memory is provided with a plurality of cache memory boards. Each of the boards is provided with a partial data array and a full tag array on each board. At least one memory address register is mounted on each of the boards with the partial data array and the full tag array for receiving a unique address from the central processing unit which enables the plurality of memory address registers to simultaneously access addresses in the partial data arrays on different boards and to also address tag addresses associated with the data addresses by sequencing controls mounted on a separate board with logic circuits which monitor output signals from the data arrays and the tag arrays. The output signals resulting from accessing memory locations in the cache memory are coupled to logic circuits for determining the type of error and the exact array where a single error has occurred.

REFERENCES:
patent: 4168541 (1979-09-01), DeKarske
patent: 4641305 (1987-02-01), Joyce et al.
patent: 4667288 (1987-05-01), Keeley et al.
patent: 4685082 (1987-08-01), Cheung et al.
patent: 4758982 (1988-07-01), Price
patent: 4831622 (1989-05-01), Porter et al.

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