Boots – shoes – and leggings
Patent
1978-03-10
1980-02-26
Malzahn, David H.
Boots, shoes, and leggings
G06F 752
Patent
active
041908945
ABSTRACT:
Apparatus for performing high-speed, parallel multiplication in a data processing system wherein each multiplication requires only one step to reduce a plurality of summands to two numbers whose summation equals the product. The fractional portion of two floating point numbers, the multiplier and the multiplicand, are coupled to registers. Thereafter, the multiplicand is multiplied by segments of the multiplier and the resultant products are summed together using a conventional shift and add means. The multiplicand and a segment of the multiplier are each coupled to a plurality of multiplier circuits which produce a plurality of summands. These summands are coupled to a plurality of counter circuits in a manner such that the digits of all of the summands representing the same power of the number 2 may be counted. The counters, using a table look-up scheme, generate two outputs which are coupled to two registers to form two numbers whose summation equals the product of the multiplicand and the segment of the multiplier.
REFERENCES:
patent: 3752971 (1973-08-01), Calhoun et al.
patent: 3795880 (1974-03-01), Singh et al.
patent: 3914589 (1975-10-01), Gaskill, Jr. et al.
Stenzel et al., "A Compact High-Speed Parallel Multiplication Scheme", IEEE Trans. on Computers, vol. C-26, No. 10, Oct. '75, pp. 948-957.
Dadda, "Some Schemes for Parallel Multipliers", IEEE Trans. on Electronic Computers, vol. EC-34, No. 5, Dec. 1965, pp. 349-356.
Wallace, "A Suggestion for a Fast Multiplier", IEEE Trans. on Electronic Computers, vol. EC-13, Feb. 1964, pp. 14-17.
Digital Equipment Corporation
Fisher Arthur W.
Malzahn David H.
Siekman Thomas C.
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