High speed parallel adder

Details High speed parallel adder High speed parallel adder

1997-09-02

2003-01-07

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S703000

Reexamination Certificate

active

06505226

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a parallel adder, and in particular, to a parallel adder that performs high speed operations.
2. Background of the Related Art
FIG. 1A
is a block diagram illustrating a related art ripple carry type adder in which a carry generated by a lower full adder is inputted as an additional input signal of an upper full adder, which is adjacent the a lower full adder. As shown in
FIG. 1A
, in a first full adder FA
10
, input signals A
0
, B
0
and a carry input signal C
in
are added to output a sum signal S
0
. A carry signal C
0
is output from the first full adder FA
10
to be an input signal for a second full adder FA
11
. The second full adder FA
11
adds input signals A
1
, B
1
, and the carry input signal C
0
to output a sum signal S
1
. The carry signal C
1
is inputted to a third full adder FA
12
as an input signal. The above-described processes are performed as many times as the prescribed number of bits.
FIG. 1B
is a block diagram illustrating a related art carry selection type adder. In an adder RCA
21
, on the assumption that there is a carry signal, an addition operation is performed. In an adder RCA
22
, on the assumption that there is not a carry signal, an addition operation is performed. As a result of the actual addition by an adder RCA
11
, the addition result of either the adder RCA
21
or the adder RCA
22
is selected and outputted through a multiplexor MUX. The addition result is selected based on whether the carry signal from the adder RCA
11
is present.
In other words, in the adder RCA
11
, four bit input signals (A
0
, B
0
), (A
1
, B
1
), (A
2
, B
2
) and (A
3
, B
3
) are added to output the carry input signal C
in
and four bit sum output signals S
0
through S
3
. Additionally, in the adder RCA
21
, on the assumption that there is a carry signal C
in
(C
in
=1), four bit input signals (A
4
, B
4
), (A
5
, B
5
), (A
6
, B
6
), (A
7
, B
7
) and a carry input signal (C
in
) are added to output four bit sum output signals S
4
through S
7
. In the adder RCA
22
, on the assumption that there is not a carry signal C
in
(C
in
=0), four bit input signals (A
4
, B
4
), (A
5
, B
5
), (A
6
, B
6
), (A
7
, B
7
) and a carry input signal C
in
(C
in
=0) are added to output and four bit sum output signals S
4
through S
7
.
When the actual addition is performed by the adder RCA
11
, the carry output signal C
out
having the value “1” may be generated, or the carry output signal C
out
may not be generated, so that the value thereof may be “0”. When the array output signal C
out
is generated, the multiplexor MUX is controlled in accordance with the carry output signal (C
out
=1), and the sum output signal of the adder RCA
21
is selected and outputted. When the carry output signal C
out
is not generated, the multiplexor MUX is controlled in accordance with the carry output signal (C
out
=0), and the sum output signal from the adder RCA
22
is selected and outputted.
FIG. 2A
is a circuit illustrating a related art full adder. In
FIG. 2A
, when input signals A and B are both high level (i.e., a logic value of “1”) and a carry signal C is high level or “1”, an OR-gate OR
1
outputs “1”, and an AND-gate AD
1
outputs “1”. In addition, a NOR-gate NOR
1
outputs “0” irrespective of the output from an AND-gate AD
2
. The output value “0” from the NOR-gate NOR
1
is inverted to “1” by an inversion buffer B
1
, and the carry signal is outputted as “1”.
FIG. 2B
is a detailed circuit diagram illustrating a related art full adder. In
FIG. 2B
, when input signals A and B are both “1”, and a carry signal C is “1”, PMOS transistors PM
1
-PM
4
are turned off. Thus, “0” is outputted from a node N
1
. The outputted value “0” from the node N
1
is inverted to “1” by an inversion buffer B
2
, and a carry signal is outputted as “1”.
In addition, a PMOS transistor PM
9
is turned on in accordance with a value “0” outputted from the node N
1
. Since PMOS transistors PM
6
-PM
8
and PMOS transistors PM
10
-PM
12
are all turned off, “0” is outputted from common nodes N
2
and N
3
. The outputted value “0” from the node N
3
is inverted to “1” by the inversion buffer B
1
, and the sum is outputted as “1”.
FIG. 3A
is a diagram illustrating an output timing of a related art ripple type adder. As shown in
FIG. 3A
, in a full adder FA
10
, input signals A
0
and B
0
and a carry input signal C
in
are added, and a delay time of &tgr;c is generated until a carry output signal C
0
is generated. In a full adder FA
11
, input signals A
1
and B
1
and a carry input signal (C
in
=C
0
) are added, and a delay time of &tgr;c is generated until the carry output signal C
1
is generated. Accordingly, a total delay time of 2&tgr;c is generated before the carry output signal C
1
.
Since the delay time of &tgr;c is generated from each full adder, a total delay time of 8&tgr;c is generated by an 8 bit ripple carry type parallel adder. In other words, since an addition operation is performed in order by the upper full adder after a carry output signal is generated by the preceding lower full adder, a relatively large amount of delay time (a processing time) is required.
FIG. 3B
is a diagram illustrating an output timing of a related art carry selection type adder. As shown in
FIG. 3B
, in the RCA
11
, four bits input signals (A
0
, B
0
), (A
1
, B
1
), (A
2
, B
2
), (A
3
, B
3
) and a carry input signal C
in
are added, and a delay time of 4&tgr;c is generated until the carry output signal C
out
is generated. However, since the remaining addition operations are performed by the adders RCA
21
and RCA
22
, a no additional delay time is required. A delay time of &tgr;c for a selection operation of the multiplexor MUX is added in accordance with a carry output signal C
out
from the adder RCA
11
. Thus, a total delay time of 5&tgr;c is generated.
The related art adders have various disadvantages. As described above, in the ripple carry type adder, since the addition operation is performed sequentially by the upper adder after a carry output signal is generated by the lower adder, the delay time is generated proportionally to the number of output bits. In the carry selection type parallel adder, since the upper adder is arranged in parallel, it is possible to slightly reduce the delay time. In other words, when a carry output is outputted from the lower adder, a predetermined result value is selected and outputted in accordance with the actual addition operation. However, the surface of the parallel adder is necessarily increased due to a laminated structure of the system.
SUMMARY OF THE INVENTION
An object of the present invention to provide a parallel adder that overcomes at least the problems and disadvantages in the related art.
Another object of the present invention to provide a parallel adder that generates a carry signal more rapidly.
A further object of the present invention is to provide a parallel adder having a reduced size/layout.
A further object of the present invention is to provide a parallel adder that selects a pass transistor after passing a carry signal through the NAND-gate/NOR-gate to reduce a layout surface when generating a sum output signal.
Still another object of the present invention is to provide a parallel adder for a digital signal processor (DSP).
To achieve the above objects, features and/or advantages in whole or in part, there is provided a parallel adder that includes a first full adder including a logic combination unit for NORing and NANDing input signals and for generating a control signal, a buffer for inverting an inverted carry input signal in accordance with the control of the logic combination unit, a carry output unit for generating a carry signal in accordance with the control of the logic combination unit and for outputting the output signal from the buffer as a carry signal, an output controller for logically combining the output signal from the logic combination unit and for generating a control signal, and a sum output unit

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