High-speed packet switching apparatus and method

Details High-speed packet switching apparatus and method High-speed packet switching apparatus and method

1990-03-26

1994-08-02

Rudolph, Rebecca L.

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364DIG1, 3642287, 364229, 364230, 364243, 3642431, 3642455, 3642459, 364246, 3642463, 3642466, 395425, G06F 1314

Patent

active

053353250

ABSTRACT:
An improved digital packet switching apparatus enabling enhanced packet transmission and high bandwidth packet transfer. The digital packet switching methods and apparatus permit selectively switching digital signal packet between a set of nodes. The invention includes multiple processing cells, each having a processor coupled to an associated content-addressable memory element. Packet processors, electrically coupled to the memory elements, selectively receive packets from the nodes and transmit the packets into at least one of the plural memory elements; or receive packets from the memory elements and transmit the packets to at least one of the nodes.

REFERENCES:
patent: 3748647 (1973-07-01), Ashany et al.
patent: 4011545 (1977-03-01), Nadir
patent: 4031512 (1977-06-01), Faber
patent: 4077059 (1978-02-01), Cordi et al.
patent: 4141067 (1979-02-01), McLagan
patent: 4245306 (1981-01-01), Besemer et al.
patent: 4293910 (1981-10-01), Flusche et al.
patent: 4334305 (1982-06-01), Girardi
patent: 4358823 (1982-11-01), McDonald
patent: 4394731 (1983-07-01), Flusche et al.
patent: 4410946 (1983-10-01), Spencer
patent: 4432057 (1984-02-01), Daniell et al.
patent: 4497023 (1985-01-01), Moorer
patent: 4503497 (1985-03-01), Krygowski et al.
patent: 4622631 (1986-11-01), Frank et al.
patent: 4700347 (1987-10-01), Rettberg et al.
patent: 4758946 (1988-07-01), Shar et al.
patent: 4792895 (1988-12-01), Tallman
patent: 4864495 (1989-09-01), Inaba
patent: 4888726 (1989-12-01), Struger et al.
patent: 4972338 (1990-12-01), Crawford
patent: 4980816 (1990-12-01), Fukuzawa et al.
patent: 5006978 (1991-04-01), Neches
patent: 5055999 (1991-10-01), Frank et al.
patent: 5060186 (1991-10-01), Barbagelato et al.
patent: 5101402 (1992-03-01), Chiu et al.
patent: 5119481 (1992-06-01), Frank et al.
Wilson, Sr. Editor, "Increased CPU Speed Drives Changes in Multiprocessor Cache and Bus Designs", Computer Design, (Jun. 1987) p. 20.
Ali et al., "Global Garbage Collection for Distributed . . . ", Int'l Jo. of Parallel Programming, vol. 15, No. 5 (1986) pp. 339-387.
Mizrahi et al., "Introducing Memory into the Switch . . . ", Proc. of the 16th Annual Int'l Symposium on Computer Archit. (1989) pp. 158-166.
Pfister et al., "The IBM Research Parallel Processor . . . ", IEEE Proc. of the 1985 Int'l Conf. on Parallel Proc. (1985) pp. 764-771.
Tabak, "Chapter 8 Bus-Oriented Systems", Multiprocessors, Prentice Hall (1990) pp. 92-102.
Gehringer et al., "The Cm* Hardware Architecture", Parallel Proc. the Cm* Experience, Digital Press, pp. 11-28, 432, 438.
Goodman et al., "The Wisconsin Multicube: A New . . . ", Proc. of the 15th Annual Int'l Symposium on Computer Archit. (1988) pp. 422-431.
Hagersten et al., "The Cache Coherence Protocol of the . . . ", Cache & Interconnect Archit. in Multiproc., Klewer Acad. Pub. (1990) pp. 165-188.
Ciepielewsik et al., "A Formal Model for Or-Parallel . . . ", Proc. of the IFIP 9th World Computer Congress (1983) pp. 299-305.
Censier et al., "A New Solution to Coherence . . . ", IEEE Transaction on Computers, vol. c-27, No. 12 (Dec. 1978) pp. 1112-1118.
Eggers et al., "Evaluating the Performance of Four . . . ", Proc. of the 16th Annual Int'l Symposium on Computer Archit. (1989) pp. 2-15.
Papamarcos et al., 1984, "A Low-Overhead Coherence Solution For Multi-Processors With Private Cache Memories", IEEE, pp. 348-354.
Schwartz, Telecommunication Networks-Protocols Modeling and Analysis, Introduction and Overview, pp. 1-20, and Layered Architectures in Data Networks, pp. 71-117, Adison-Wesley, 1987.
"Multi-Microprocessors: and Overview . . . " IEEE vol. 26 #2, pp. 216-228.
"Cm*-A Modular Multi-Microprocessor," Nat'l Comp Confr '77, 637-644.

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