High speed packet switch

Details High speed packet switch High speed packet switch

1996-01-16

1998-05-26

Kizou, Hassan

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370417, H04L 1256

Patent

active

057577994

ABSTRACT:
A high speed packet switch which is inherently non-blocking, requires a minimum amount of buffering, is modular and degrades gracefully with failures. The output destination buffers can each absorb data at the full switch rate to avoid contention and they are filled evenly to minimize buffer size. The architecture only requires few parts types (multiplexers, demultiplexers and crosspoint switches) to operate at high speeds. The output list offers considerable flexibility in the way the data is output, whether it is by priority and/or by time division multiplexed sub destinations.

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