High-speed packet memory

Multiplex communications – Pathfinding or routing – Store and forward

Reexamination Certificate

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Details

C370S369000, C711S001000, C711S101000

Reexamination Certificate

active

07126959

ABSTRACT:
A high-speed packet memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into [X/N] groups of cells;a read-write control block comprising a means for receiving cells from the write port and storing each cell, which belongs to the same group, in a selected different one of the N memory modules at the same memory address (the group address);a multi-cell pointer (MCP) storage for storing an MCP for said group of cells (an associated MCP) at an MCP address, the MCP having N memory module identifiers to record the order in which cells of said group of cells are stored in the N memory modules; andthe MCP address being the same as the group address. Corresponding methods for storing cells and/or storing and retrieving variable size packet in such memory are also provided.

REFERENCES:
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patent: 6160814 (2000-12-01), Ren et al.
patent: 6314489 (2001-11-01), Nichols et al.
patent: 6356546 (2002-03-01), Beshai
Iyer, S., et al, “Techniques for Fast Shared Memory Switches”, Unpublished Manuscript, Stanford University, Sep. 2001.
Kumar, S., et al, Implementing Parallel Packet Buffering, Part I (CommsDesign, Apr. 22, 2002).
Kumar, S., et al, Implementing Parallel Packet Buffering, Part II (CommsDesign, Apr. 29, 2002).

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