High speed output buffer

Details High speed output buffer High speed output buffer

2001-08-29

2002-08-06

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Nonlinear amplifying circuit

C327S053000, C327S112000, C330S252000, C330S264000, C330S288000, C330S311000

Reexamination Certificate

active

06429735

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to high-speed output buffers. More particularly, the present invention relates to an apparatus for an output buffer that has low capacitive loading and high-speed operation with improved symmetry.
BACKGROUND OF THE INVENTION
Differential amplifiers are often employed to isolate a signal path from one or more output terminals in a circuit. A conventional differential amplifier (
600
) is illustrated in FIG.
6
. As shown in the figure, the conventional differential amplifier (
600
) includes two NMOS transistors (M
610
-M
611
), three PMOS transistors (M
612
-M
614
), two current sources (I
60
, I
61
), and an inverter (XINV).
Transistor M
610
includes a gate that is connected to a non-inverting input terminal (INP), a drain that is connected to node N
63
, and a source that is connected to node N
62
. Transistor M
611
includes a gate that is connected to an inverting input terminal (INM), a drain that is connected to node N
64
, and a source that is connected to node N
62
. Transistor M
612
includes a gate and drain that are connected to node N
63
, and a source that is connected to a high power supply terminal (VDD). Transistor M
613
includes a gate that is connected to node N
63
, a drain that is connected to node N
64
, and a source that is connected to VDD. Transistor M
614
includes a gate that is connected to node N
64
, a drain that is connected to node N
65
, and a source that is connected to VDD. Current source I
60
is connected between nodes N
62
and VSS. Current source I
61
is connected between nodes N
65
and VSS. Inverter XINV has an input that is connected to node N
65
, and an output that is connected to an output terminal (OUT).
In operation, a differential input voltage is applied across the non-inverting and inverting input terminals (INP, INM). Transistors M
610
and M
611
are a differential pair that is arranged to provide a first gain stage for amplifying the differential input voltage. Node N
64
is a high gain node that is used as an output of the first gain stage. Transistor M
614
and I
61
are arranged to operate as a second gain stage, further amplifying the signal from node N
64
. Inverter XINV operates as a third gain stage. Inverter XINV provides a single-ended output signal at the output terminal (OUT).
SUMMARY OF THE INVENTION
The present invention is directed to high-speed output buffers. More particularly, the present invention relates to an apparatus and for an output buffer that has low capacitive loading and high-speed operation with improved symmetry.
Briefly described below is an apparatus for an improved output buffer includes a symmetrical pre-gain stage and a gain stage. The pre-gain stage includes a pair of matched differential amplifiers that are arranged to provide a differential intermediary signal. The gain stage is arranged to receive the differential intermediary signal and provide a single-ended output signal. The pre-gain stage differential amplifiers include transistors that are arranged as differential pairs, where each of differential pair transistors is minimally sized to provide very low capacitive loading. The pre-gain stage differential amplifiers are matched such that symmetrical amplification is obtained from the differential intermediary signal. The pre-gain stage arrangement provides for a differential intermediary signal such that common-mode noise rejection and power supply noise rejection are enhanced. The improved output buffer operates at high frequencies that are well into the gigahertz operating range, while maintaining reasonably high-gain and very low distortion in the signal symmetry.
An apparatus that provides a buffered output signal in response to a differential input signal that is provided by an electronic circuit is also described below. The apparatus includes a pre-gain stage amplifier that is arranged to provide a differential intermediary signal in response to the differential input signal. The pre-gain stage amplifier includes a first differential amplifier that provides a first half of a gain associated with the pre-gain amplifier and a second differential amplifier that provides a second half of the gain of the pre-gain stage amplifier. A gain stage amplifier provides the buffered output signal in response to the differential intermediary signal. The input impedance of the pre-gain stage amplifier has a low input capacitance such that the performance of the electronic circuit is unaffected by the apparatus.
In one example, an apparatus is described below that includes a first and second differential amplifier, and a transconductance amplifier. The first amplifier includes a first non-inverting input, a first inverting input, and a first output. A differential input signal is coupled across the first non-inverting input and the first inverting input. The second differential amplifier includes a second inverting input that is coupled to the first non-inverting input, a second non-inverting input that is coupled to the first inverting input, and a second output. The transconductance amplifier includes a third non-inverting input that is coupled to the first output, and a third inverting input that is coupled to the second output. The first and second differential amplifiers provide an intermediary differential signal across the first output and the second output. The transconductance amplifier provides the buffered output signal at the third output in response to the intermediary differential signal.
In another example, an apparatus is described below that includes a first means for amplifying and a second means for amplifying. The first means for amplifying is arranged to provide a differential intermediary signal by differentially amplifying the differential input signal. The differential intermediary signal rejects common-mode signals. The first means for amplifying includes a means for receiving that is arranged to receive the differential input signal while minimizing capacitive loading on the electronic circuit. The second means for amplifying is arranged to provide the buffered output signal by amplifying the differential intermediary signal.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detailed description of illustrative embodiments of the invention, and to the appended claims.


REFERENCES:
patent: 4845672 (1989-07-01), Watanabe et al.
patent: 5682119 (1997-10-01), Soda
patent: 6242980 (2001-06-01), Tsukagoshi et al.
patent: 6285256 (2001-09-01), Wong

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