High speed operable semiconductor memory device with memory bloc

Details High speed operable semiconductor memory device with memory bloc High speed operable semiconductor memory device with memory bloc

1998-07-07

2000-06-06

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

365233, G11C 800

Patent

active

060727438

ABSTRACT:
A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.

REFERENCES:
patent: 5640362 (1997-06-01), Yoo
patent: 5666322 (1997-09-01), Conkle
patent: 5812490 (1998-09-01), Tsukude
patent: 5894448 (1999-04-01), Amano et al.
"A 1.6GB/s Data-Rate 1Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture", Y. Nitta et al., 1996 IEEE International Solid-State Circuits Conference 1996 Digest of Technical Papers.
"Super LSI Memory", K. Ito, published by Baifukan, pp. 19.

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