High speed operable semiconductor memory device with memory...

Details High speed operable semiconductor memory device with memory... High speed operable semiconductor memory device with memory...

2000-01-06

2001-04-10

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S051000, C365S063000, C365S233100

Reexamination Certificate

active

06215720

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to an arrangement of memory blocks in a semiconductor memory device and an arrangement of a peripheral circuit thereof.
2. Description of the Background Art
Increase in the capacity of a semiconductor memory device, particularly in a dynamic random access memory (DRAM), has seen significant development. A DRAM is a versatile memory that is often incorporated in a standard memory module (SIMM: single in-line memory module; DIMM: dual in-line memory module).
FIG. 27
shows an example of a memory block arrangement of a 64-Mbit DRAM. Such a DRAM is disclosed in, for example, FIG. 1.14 on page 19 in “Super LSI Memory” by Kiyoh Ito published by Baifukan.
Referring to
FIG. 27
, the DRAM includes a semiconductor substrate
2000
, and memory blocks MB
16
a
, MB
16
b
, MB
16
c
and MB
16
d
of 16M bits formed on semiconductor substrate
2000
.
Each of memory blocks MB
16
a
-MB
16
d
includes a column decoder CDa and row decoder RRCa.
In the DRAM shown in
FIG. 27
, four 16-Mbit memory blocks having an aspect ratio of approximately 1:2 are arranged in two rows and two columns. Therefore, semiconductor substrate
2000
has an aspect ratio of approximately 1:2.
In the center region CRS extending from the center of one short side of semiconductor substrate
2000
towards the center of the opposite short side of semiconductor substrate
2000
are arranged an input/output interface circuit (not shown) and pads for input and output. In the center region CRL extending from the center of one long side to the center of the opposite long side of semiconductor substrate
2000
are arranged a peripheral circuit for the control of the memory array.
The input/output interface circuit functions to convert an externally applied control signal and write data into internal signals and supply the internal signal to a control circuit. The input/output interface circuit also provides the readout data transferred from a memory block to a control circuit to an external source.
The peripheral circuit provides control of a memory block according to a control signal or data applied to the input/output interface circuit.
The 16-Mbit memory block is internally divided into a plurality of subblocks (not shown). The 16-Mbit memory block includes a row decoder of the X direction and a column decoder of the Y direction.
At the current stage, a DRAM package has an aspect ratio of approximately 1:2. This is attributed to the aspect ratio of 1:2 of the DRAM chip.
FIG. 28
is a diagram for describing the configuration of a memory cell of a DRAM formed of the general one transistor-one capacitor.
Referring to
FIG. 28
, a memory cell MC includes a capacitor MQ
1
connected between a cell plate CP and a storage node SN
1
for storing information, and an access transistor MT
1
for connecting storage node SN
1
with a bit line BL. Bit line BL is connected to a sense amplifier SA together with a bit line /BL which is the counter electrode. When word line WL
1
is activated so that the information stored in capacitor MQ
1
is read out to bit line BL, the sense amplifier amplifies the potential difference between bit lines /BL and BL to output data.
Although only one bit line BL is connected to one memory cell, another bit line /BL which is a counter electrode is required to read out data from the memory cell. Therefore, it is typical to form a memory cell of 1 bit with one word line and one pair of bit lines (bit lines BL and /BL) in implementing a memory array. Since the word line and the bit lines are fabricated under the smallest rule, the aspect ratio of a 1-bit memory cell is approximately 1:2.
FIGS. 29A and 29B
are schematic diagrams for describing the configuration of memory blocks.
Memory blocks D
44
and D
28
show the formation of memory blocks having a plurality of memory cells corresponding to 2 to the m-th power bits where m is an even number. Memory block D
44
has memory cells of the aspect ratio of 1:2 arranged in four rows and four columns. Memory block D
28
has memory cells arranged in 8 rows and 2 columns.
The memory blocks have a ratio of a longer side to the shorter side of 2:1.
Memory blocks D
42
and D
24
show formation of memory blocks having a plurality of memory cells corresponding to 2 to the m-th power bits where m is an odd number. Memory block D
42
has memory cells arranged in 2 rows and 4 columns. In this case, the ratio of the longer side to the shorter side of the memory block is 4:1. Memory block D
24
has memory cells arranged in 4 rows and 2 columns. In this case, the memory block has substantially a square configuration.
When a DRAM is incorporated into the memory module, it is desirable to accommodate the DRAM in the same package even if the capacity of the DRAM is large. For example, the chip size of the DRAM per se is reduced by the advanced technique of microminiaturization to be accommodated into a package of the same size even when the capacity of the DRAM is fourfold from 4M bits to 16M bits.
A package of a different size induces the need to fabricate different module substrates corresponding to each size. If the size of the package for a DRAM of a higher generation with a larger capacity can be suppressed to a level identical to that of a conventional package, the conventional module substrate can be used without any great modification (or with only a slight modification). This is advantageous in the fabrication of a memory module of a great capacity.
However, it is expected that the technological advance in microminiaturization for achieving a chip size that allows a 256-Mbit DRAM of a generation succeeding the current 64-Mbit DRAM to be accommodated in a chip of a size (400 mil-width package) identical to the size of the current 64-Mbit DRAM will not yet be available for some time.
At the present stage, it is convenient if a DRAM having a capacity of 128M bits can be accommodated in a package of a size identical to that of the current 64-Mbit DRAM.
Consider the configuration of a 128-Mbit DRAM chip. Since the 128-Mbit DRAM has a capacity of 2 to the m-th power bits where m is an odd number, it is difficult to achieve an aspect ratio of 1:2 by a normal fabrication process as described above.
FIGS. 30 and 31
are diagrams for describing the array configuration of a 128-Mbit DRAM.
Referring to
FIG. 30
, two of a 64-Mbit memory block MB
64
having an aspect ratio of 1:2 are arranged laterally in one row on a semiconductor substrate
2100
. Such an arrangement will result in a 128-Mbit DRAM of a chip configuration having an aspect ratio of 1:4.
Referring to
FIG. 31
, 64-Mbit memory blocks MB
64
are arranged vertically in one column on a semiconductor substrate
2200
. Such an arrangement will result in a 128-Mbit DRAM having a square chip with an aspect ratio of 1:1.
If the 128-Mbit DRAM is to be accommodated in a general 64-Mbit DRAM package having an aspect ratio of approximately 1:2, microminiaturization of an extremely high level is required. More specifically, a shrink rate of approximately two times smaller than that in fabricating a 64-Mbit DRAM will be required. This is not easy to realize.
FIG. 32
is a diagram for describing an arrangement of a conventional peripheral circuit of a DRAM.
The DRAM includes a semiconductor substrate
2300
, memory blocks MBn arranged in two rows and two columns on semiconductor substrate
2300
, power supplies IPS
1
and IPS
2
arranged in a center region CRS corresponding to the shorter sides of semiconductor substrate
2300
, a data input/output interface DI, an address input buffer ABUF, a clock buffer CKB, a PLL circuit PL receiving a clock from clock buffer CKB for generating an internal clock of the same phase, and a control circuit CC arranged at a center region CRL corresponding to the longer side of semiconductor substrate
2300
.
In such a chip arrangement, PLL circuit PL cannot always be placed at a position having equal distance from all the memory blocks. There is a possibility that the t

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