High-speed offset comparator

Details High-speed offset comparator High-speed offset comparator

2000-08-16

2002-06-04

Shingleton, Michael B (Department: 2817)

Amplifiers

With periodic switching input-output

C327S307000, C330S253000, C330S258000

Reexamination Certificate

active

06400219

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits and particularly to comparators used in high-speed applications.
2. Description of the Related Art
The function of a voltage comparator is to compare the instantaneous value of a signal voltage at one input to that of a voltage, often a reference voltage, at a second input and produce a voltage representing a digital value, i.e., a binary 1 or 0, at the output when one input is higher than the other.
FIG. 1
a
shows the characteristics of a comparator
10
with inputs V
ip
and V
in
and output V
o
, where all the signal levels are measured with reference to circuit ground. In this case, when the differential input voltage V
id
=V
ip
−V
in
exceeds 0 volts, the output switches from 0 volts, which is binary 0, to V
dd
volts, which is binary 1, as shown by the transfer curve.
Offset comparators have a certain built-in offset voltage V
T
associated with the differential input such that when the differential input signal exceeds this threshold, the output switches binary states.
FIG. 1
b
shows a comparator
15
with a built-in threshold V
T
. In this case, when the differential input voltage V
id
exceeds the offset threshold V
T
, the output switches binary states. As illustrated in the accompanying transfer curve, the differential input voltage V
id
has to exceed the threshold voltage (V
T
) before the output switches form 0 to V
dd
.
Two conventional approaches for establishing this built-in offset voltage are discussed below. The first approach is illustrated in FIG.
2
.
FIG. 2
is a schematic diagram of an offset comparator that uses a common-mode tracking circuit to provide the threshold voltage V
T
. The circuit is comprised of an operational amplifier made up of two differential n-channel input transistors
22
-
23
, a tail current source
24
, two p-channel load transistors
20
-
21
, a differential offset circuit consisting of two additional differential n-channel input transistors
25
-
26
, a second tail current source
27
, and a common-mode tracking circuit
28
. The differential input signals, V
ip
and V
in
, are applied to both the operational amplifier's inputs at the gates of n-channel transistors
22
-
23
and to the differential inputs of the common-mode tracking circuit
28
. The difference in the output signals from the common-mode tracking circuit
28
, V
B1
and V
B2
, represents the offset threshold voltage V
T
. These V
B1
and V
B2
signals are inputs to the second differential pair consisting of n-channel transistors
25
and
26
, respectively. Finally, the drains of transistors
25
-
26
are coupled to the drains of the operational amplifier differential pair transistors
22
-
23
to establish an offset.
Thus, in the first approach the desired offset voltage is accomplished by means of adding another differential pair
25
-
26
, with its own separate tail current
27
, in parallel to the input differential pair
22
-
23
of a 0-volt offset comparator. The added pair
25
-
26
should be identical to the input differential pair
22
-
23
of the 0-volt offset comparator, as should the tail currents
24
,
27
. A common-mode tracking circuit
28
is needed to supply the two bias voltages V
B1
and V
B2
. This common-mode tracking circuit is called on to supply the V
B1
and V
B2
inputs such that V
B1
−V
B2
is equal to the desired offset V
T
, and at the same time such that V
B1
and V
B2
have the same common-mode level as the original inputs, V
ip
and V
in
.
The second approach for establishing this built-in offset voltage is illustrated in FIG.
3
. This approach uses two resistor networks
31
-
34
and
35
-
38
at the inputs of a operational amplifier
30
. In this case, each resistor network,
31
-
34
and
35
-
38
, is connected between the V
dd
voltage and circuit ground with voltage taps located between each resistor. In operation, the differential inputs V
ip
and V
in
are connected to taps on the respective resistor networks, while the + and − differential inputs to the operational amplifier
30
are taken off other resistor network taps to provide the desired offset for the comparator. This circuit has the characteristics of low input-impedance and high power dissipation.
The offset comparators discussed above either have a common-mode tracking circuit, or have low input impedance. The common-mode tracking circuit is very slow and not suitable if the differential input signal has a fast changing common-mode. On the other hand, the resistor network dissipates a great amount of power and gives a low input-impedance characteristic to the comparator. The above-described prior art circuits are also not directly compatible with many low-voltage digital applications and usually need another circuit to step down the output signal to the desired digital levels. Thus, they tend to be slow, dissipate too much power, and are not directly compatible with many low-voltage digital applications; one such example being the USB interface for computers.
What is needed is a high-speed comparator with a high input-impedance characteristic that can track high-speed differential signals with rapidly changing common-mode levels and provide a binary output signal that can directly interface with inputs of low-voltage applications. The invention disclosed herein addresses these needs and provides such a circuit.
SUMMARY OF THE INVENTION
In accordance with the present invention there is provided a high-speed differential offset comparator circuit, providing a comparator function at a predetermined offset voltage. The differential offset comparator circuit includes a substantially zero offset comparator circuit having a first and a second differential input. The differential offset comparator circuit also includes a first pre-amplifier circuit and a second pre-amplifier circuit having an output coupled to the first and the second differential input, respectively, of the substantially zero offset comparator circuit. The pre-amplifier circuits are capable of providing a controllable offset to the differential offset comparator circuit. Each pre-amplifier circuit includes a first MOS transistor and a second MOS transistor connected in series to form a first composite transistor having an effective source, gate and drain. The first MOS transistor receives an input of the differential offset comparator circuit at a gate thereof. The second MOS transistor receives a control voltage corresponding to an offset control voltage at a gate thereof. The offset control voltage controls the value of the predetermined offset voltage.
Circuits according to the present invention can track high-speed signals with rapidly changing common-mode levels without the need for a common-mode tracking circuit, while providing a high impedance input.


REFERENCES:
patent: 3959733 (1976-05-01), Solomon et al.
patent: 3980963 (1976-09-01), Doi
patent: 5231351 (1993-07-01), Kordts et al.
patent: 5506544 (1996-04-01), Staudinger et al.
Todd “FETs as voltage-variable resistors” Application Notes vol. 13 No. 19 pp 66-69 Sep. 13, 1965.*
Mel Bazes, “Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers,” IEEE Journal of Solid-State Circuits, vol. 26, No. 2, pp. 165-168, Feb. 1991.

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