High speed numerical processor for performing a plurality of num

Details High speed numerical processor for performing a plurality of num High speed numerical processor for performing a plurality of num

1989-04-26

1991-09-10

Shaw, Dale M.

Boots, shoes, and leggings

364752, 364761, G06F 752, G06F 738

Patent

active

050479733

ABSTRACT:
Division and square root calculations are performed using an operand routing circuit (16) for receiving an operand N, and operand D and a seed value S and directing the operands and seed value to a multiplier (38). Single multiplier (38) is configured into two arrays for calculating partial products of N and S and D and S. The results of multiplier (38) are transmitted through switching circuitry (20) or registers (48) (50) either to operand routing circuitry (16) or adder (44) depending on a convergence algorithm. The final result is rounded.

REFERENCES:
patent: 3535498 (1970-10-01), Smith, Jr.
patent: 4754421 (1988-06-01), Bosshart
patent: 4825401 (1989-04-01), Ikumi
Agrawal, "High-Speed Arithmetic Arrays", IEEE Trans. on Computers, vol. C-28, #3, pp. 215-224, Mar. 1979.
Zurawski, "Design of High-Speed Digital Divider Units", IEEE Trans. on Computers, vol. C-30, #9, pp. 691-699, 9/81.
Computer Arithmetic, by Kai Huang, John Wiley & Sons, pp. 252-259.

Affiliated with

Also associated with

Rating

High speed numerical processor for performing a plurality of num does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed numerical processor for performing a plurality of num, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed numerical processor for performing a plurality of num will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-545680