High speed non-return-to-zero digital clock recovery apparatus

Details High speed non-return-to-zero digital clock recovery apparatus High speed non-return-to-zero digital clock recovery apparatus

1988-05-06

1989-04-04

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

331 1A, 328 74, H03L 700

Patent

active

048192511

ABSTRACT:
A digital clock recovery circuit is presented which uses a delay line to produce a plurality of delayed sample signals. The sample signals are used to sample incoming data in a phase detector and the resultant sampled data is then resampled by the tentatively correct apparatus clock output signal. The resampled data provides a direct indication of the phase difference beween the data and the clock and the value can be obtained using a summing circuit. If the summed amount is outside an allowable range of values, a phase altering signal is supplied to an oscillator to change the phase of the apparatus clock output signal.

REFERENCES:
patent: 3935538 (1976-01-01), Kizler et al.
patent: 4641323 (1987-02-01), Tsang
patent: 4733197 (1988-03-01), Chow

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