High speed network switch bus clock

Details High speed network switch bus clock High speed network switch bus clock

1998-07-01

2002-11-12

Vanderpuye, Ken (Department: 2661)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S503000

Reexamination Certificate

active

06480498

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to transmitting data over a bus, and more specifically to transmitting a clock signal over the bus.
BACKGROUND OF THE INVENTION
Local Area Networks (LANs) are commonly used to interconnect computers or other devices. One computer may transmit a packet of data to another computer over the network. The packet includes a source address field, a destination address field, a data field, and other fields. The destination address field is used to route the packet to the appropriate destination.
A LAN may grow to include a large number of devices and to reach a large physical area. For example, a large number of personal computers may be interconnected over a LAN. The personal computers may be spread across a number of locations. As the number of devices increase so too does the demand for network bandwidth. As the distance between devices increases so to does signal degradation.
Network devices such as routers, hubs, switches, bridges, repeaters and others may be used to divide network traffic and boost network signals. For example, a network switch may be used to divide a network into sub-networks. As a packet may not need to be transmitted to every sub-network, the switch routes the packet to the appropriate sub-network (i.e. the sub-network having a device address which matches the packet's destination address). In this way, a switch is able to reduce traffic within a sub-network.
Such a switch requires a bus operative to route packet data to the appropriate sub-network. However, as each of the sub-networks may simultaneously transmit data, the bandwidth of the bus should exceed that of the sub-networks. For example, typical network devices are capable of transmitting data at 100 Mb/s. Where a large number of such devices are interconnected through a switch, the bus must operate at a relatively high speed.
A high-speed bus requires a clock signal so that data may be properly detected by receiving devices connected to the bus. As the bus operates at a high-speed, the clock signal may produce significant levels of electromagnetic interference (EMI). For example, on a bus operating at 100 Mbps with a corresponding clock signal at 100 MHz, both the data signals and the clock signal may produce significant levels of EMI. As EMI acts to degrade data signals and to interfere with other nearby circuitry, such EMI should be minimized.
A bus cable typically exhibits a low pass filter characteristic. Such a characteristic operates to delay higher-frequency signals more than lower frequency signals. As data signals exhibit a random distribution, they do not necessarily change state at each transition. Accordingly, a 100 Mbps data line will on average operate at a frequency lower than 100 MHz. Accordingly, the 100 MHz clock will experience more delay than the average data signals. As the clock is used to make sampling decisions on the data lines, the delay produces sub-optimal sampling.
Accordingly, a bus is desired which acts to effectively transmit data between sub-networks. The bus must operate to reduce the potential for transmission errors while at the same time provide adequate bandwidth to service a plurality of network devices. Moreover, the bus should operate to minimize EMI over the data bus and with other nearby circuitry.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a data bus for transmitting data between a plurality of devices includes a plurality of data lines and a clock line. The plurality of data lines are configured to connect with a plurality of devices and to convey data signals at a bit rate between the plurality of devices. The clock line is configured to connect with the plurality of devices and to convey a clock signal at a fraction of the bit rate between the plurality of devices.
According to another aspect of the invention, a network device configured to convey data between a bus and a port includes a plurality of data paths, a clock path and a memory. The plurality of data paths are configured to receive data signals at a bit rate from other network devices. The clock path is configured to receive a clock signal at a fraction of the bit rate from the other network devices. The memory is operationally coupled with the plurality of data lines and the clock line. The memory has a first portion and a second portion. The memory is configured to receive one byte of data into the first portion after a first transition in the clock signal and to receive another byte of data into the second portion after a second transition in the clock signal.
According to another aspect of the invention, packet data is transmitted over a bus. The transmission includes transmitting a first data signal over a data bus at a bit rate. The transmission also includes transmitting a clock signal over a clock line at a fraction of the bit rate wherein the clock signal passes through a first transition during transmission of the first data signal. The transmission further includes transmitting a second data signal over the data bus wherein the clock signal passes through a second transition during transmission of the second data signal.
According to another aspect of the invention, a method of receiving packet data over a bus includes receiving a first data signal at a bit rate over the bus. The method also includes receiving a second data signal at the bit rate over the bus. The method further includes receiving a clock signal at a fraction of the bit rate over the bus. The method further includes sampling the first data signal during a first transition in the clock signal. The method further includes sampling the second data signal during a second transition in the clock signal, wherein the second transition occurs immediately following the first transition.


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“High-Performance Bus Interface Designer's Guide (Futurebus+, PI-Bus, BTL)”; National Semiconductor Corporation, Santa Clara, California; pp. 1-80—1-93; 1992 Edition.

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