Multiplex communications – Wide area network – Packet switching
Patent
1995-01-25
1996-06-11
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370108, 327407, 327415, H04J 304
Patent
active
055263607
ABSTRACT:
A high-speed burst digital time multiplexed data system has N parallel input data paths that are multiplexed onto a serial data path for transmission from a transmitter to a receiver. Serial transmission takes place in a short burst upon command at the transmitter. Data from the serial data path is demultiplexed back into N parallel data paths at the receiver. The entire process is accomplished asynchronously without the aid of a clock or framing signal. In the preferred embodiment, a train of N sampling pulses is generated by two tapped delay lines, one at the transmitter and one at the receiver. The length of each sequential sampling pulse is determined by the tap spacing of the delay line, and the duration of the entire burst process is equal to the total delay of the delay line. A new burst may be initiated at any time after the completion of the previous burst. Thus bursts may follow each other immediately or be arbitrarily spaced to occur whenever data transmission is required.
REFERENCES:
patent: 2953694 (1960-09-01), Wilson
patent: 3496546 (1970-02-01), Villafana et al.
patent: 3959767 (1976-05-01), Smither et al.
patent: 4027301 (1977-05-01), Mayer
patent: 4208724 (1980-06-01), Rattlingourd
patent: 4410980 (1983-10-01), Takasaki et al.
patent: 4451819 (1984-05-01), Beckenhauer
patent: 4485470 (1984-11-01), Reali
patent: 4513427 (1985-04-01), Borriello et al.
patent: 4680759 (1987-07-01), Miller et al.
patent: 4763327 (1988-08-01), Fontaine et al.
patent: 4779268 (1988-10-01), Wissman
patent: 4841522 (1989-06-01), Yamazaki
patent: 4899339 (1990-02-01), Shibagaki et al.
patent: 5091907 (1992-02-01), Woltengel
patent: 5111455 (1992-05-01), Negus
patent: 5136587 (1992-08-01), Obanu et al.
patent: 5150364 (1992-09-01), Negus
Nakamura, H., et al.; "2GHz Multiplexer and Demultiplexer Using DCFL/SBFL Circuit and the Precise V.sub.th Control Process"; IEEE GA AS IC Symposium, 1986; pp. 151-154.
Jeong, D; et al.; "Design of PLL-Based Clock Generation Circuits" IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr., 1987; pp. 255-261.
Bayruns, R. J., et al.; "A Fine-Line NMOS 3-Gbit/s 12-Channel Time-Division Multiplexer/Demultiplexer Chip Set"; IEEE Journal of Solid State Circuits, vol. 24, No. 3, Jun., 1989; pp. 814-821.
Dade International Inc.
MacLean Kurt A.
Olms Douglas W.
Patel Ajit
LandOfFree
High speed N-to-1 burst time-multiplexed data transmission syste does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High speed N-to-1 burst time-multiplexed data transmission syste, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed N-to-1 burst time-multiplexed data transmission syste will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-359556