High speed multiplier which divides multiplying factor into part

Details High speed multiplier which divides multiplying factor into part High speed multiplier which divides multiplying factor into part

1990-02-09

1991-12-03

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

050704710

ABSTRACT:
A multiplier for multiplying two binary operands is presented which comprises an encoding unit, a multiplying unit composed of two multiplying arrays, and a logic unit. The encoding unit to which the second operand is applied generates factors following the Booth algorithm. The two multiplying arrays are respectively applied with the first operand as well as with factors belonging to the higher significance digits or the lower significance digits, respectively, of the second operand. In both multiplying arrays the multiplication of the factors with the first operand into a respective partial end product is simultaneously performed. Both partial end products are applied to the logic unit which generates therefrom the end product in accordance with the algorithm used at the beginning.

REFERENCES:
patent: 4484301 (1984-11-01), Borgerding et al.
patent: 4525796 (1985-06-01), Omoda et al.
patent: 4799183 (1989-01-01), Nakano et al.
patent: 4817029 (1989-03-01), Finegold
patent: 4831577 (1989-05-01), Wei et al.

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